參數(shù)資料
型號(hào): ISP1161A1BM,557
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 127/137頁
文件大?。?/td> 599K
代理商: ISP1161A1BM,557
Philips Semiconductors
ISP1161A1
USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
8 of 136
9397 750 13961
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
D6
6
I/O
bit 6 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D7
7
I/O
bit 7 of bidirectional data; slew-rate controlled; TTL input;
three-state output
DGND
8
-
digital ground
D8
9
I/O
bit 8 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D9
10
I/O
bit 9 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D10
11
I/O
bit 10 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D11
12
I/O
bit 11 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D12
13
I/O
bit 12 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D13
14
I/O
bit 13 of bidirectional data; slew-rate controlled; TTL input;
three-state output
DGND
15
-
digital ground
D14
16
I/O
bit 14 of bidirectional data; slew-rate controlled; TTL input;
three-state output
D15
17
I/O
bit 15 of bidirectional data; slew-rate controlled; TTL input;
three-state output
DGND
18
-
digital ground
Vhold1
19
-
voltage holding pin; internally connected to the Vreg(3.3) and
Vhold2 pins. When VCC is connected to 5 V, this pin will
output 3.3 V, hence do not connect it to 5 V. When VCC is
connected to 3.3 V, this pin can either be connected to
3.3 V or left unconnected. In all cases, decouple this pin to
DGND.
n.c.
20
-
no connection
CS
21
I
chip select input
RD
22
I
read strobe input
WR
23
I
write strobe input
Vhold2
24
-
voltage holding pin; internally connected to the Vreg(3.3) and
Vhold1 pins. When VCC is connected to 5 V, this pin will
output 3.3 V, hence do not connect it to 5 V. When VCC is
connected to 3.3 V, this pin can either be connected to
3.3 V or left unconnected. In all cases, decouple this pin to
DGND.
DREQ1
25
O
HC DMA request output (programmable polarity); signals
to the DMA controller that the ISP1161A1 wants to start a
DMA transfer; see Section 10.4.1
DREQ2
26
O
DC DMA request output (programmable polarity); signals
to the DMA controller that the ISP1161A1 wants to start a
DMA transfer; see Section 13.1.4
DACK1
27
I
HC DMA acknowledge input; when not in use, this pin must
be connected to VCC via an external 10 k resistor
Table 2:
Pin description for LQFP64…continued
Symbol[1]
Pin
Type
Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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