參數(shù)資料
型號(hào): ISP1161A1BM,557
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 11/137頁
文件大?。?/td> 599K
代理商: ISP1161A1BM,557
Philips Semiconductors
ISP1161A1
USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
107 of 136
9397 750 13961
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
13.3.6
Read Interrupt register (R: C0H)
This command indicates the sources of interrupts as stored in the 4-byte DcInterrupt
register. Each individual endpoint has its own interrupt bit. The bit allocation of the
DcInterrupt register is shown in Table 108. Bit BUSTATUS is used to verify the current
bus status in the interrupt service routine. Interrupts are enabled via the
DcInterruptEnable register, see Section 13.1.5.
Remark: While reading the DcInterrupt register, read both 2 bytes.
Code (Hex): C0 — read interrupt register
Transaction — read 2 words
Remark: For details on interrupt control, see Section 8.6.3.
Table 107: DcChipID register: bit description
Bit
Symbol
Description
15 to 8
CHIPIDH[7:0]
chip ID code (61H)
7 to 0
CHIPIDL[7:0]
silicon version (23H, with 23 representing the BCD encoded
version number)
Table 108: DcInterrupt register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
Reset
00H
Access
R
Bit
23
22
21
20
19
18
17
16
Symbol
EP14
EP13
EP12
EP11
EP10
EP9
EP8
EP7
Reset
00000000
Access
RRRRRRRR
Bit
15
14
13
12
11
10
9
8
Symbol
EP6
EP5
EP4
EP3
EP2
EP1
EP0IN
EP0OUT
Reset
00000000
Access
RRRRRRRR
Bit
7
6
5
4
3
2
1
0
Symbol
BUSTATUS
SP_EOT
PSOF
SOF
EOT
SUSPND
RESUME
RESET
Reset
00000000
Access
RRRRRRRR
Table 109: DcInterrupt register: bit description
Bit
Symbol
Description
31 to 24
-
reserved
23 to 10
EP14 to EP1
A logic 1 indicates the interrupt source(s): endpoint 14 to 1.
9
EP0IN
A logic 1 indicates the interrupt source: control IN endpoint.
8
EP0OUT
A logic 1 indicates the interrupt source: control OUT endpoint.
7
BUSTATUS
Monitors the current USB bus status (0 = awake, 1 = suspend).
6
SP_EOT
A logic 1 indicates that an EOT interrupt has occurred for a short
packet.
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