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參數(shù)資料
| 型號(hào)： | IS82C600 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 64K x 16 High-Speed SRAM with Address Decoding and Ready Logic(帶地址譯碼器和預(yù)備邏輯的高速靜態(tài)RAM) |
| 中文描述： | 64K的× 16高速的地址譯碼和就緒邏輯（帶地址譯碼器和預(yù)備邏輯的高速靜態(tài)RAM的靜態(tài)存儲(chǔ)器） |
| 文件頁數(shù)： | 4/21頁 |
| 文件大?。?/td> | 129K |
| 代理商： | IS82C600 |
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY
TB001-0B
01/20/99
IS82C600
ISSI
PIN INFORMATION
Complete pin information on the device is organized as
follows:
Overview
Conventions
Pin Diagram
Pin Assignment Table—Arranged by Pin Number
Pin Assignment Table—Arranged by Ball Location
Detailed Pin Descriptions
Overview
The R/
W
signal determines the direction of the bus
transaction.
Some processors, including TI TMS320LC54X, have three
major memory spaces. Program Space (
PS
); Data Space
(
DS
); and I/O Space (
IS
). The Memory Space signals (
DS
,
PS
, and
IS
) select the memory address space being
accessed (Data, Program, or I/O). No more than one of the
Memory Space signals can be asserted at the same time.
Data or Program spaces (or any part of these spaces) can
be mapped into either internal SRAM of the TrailBlazer or
any external devices. I/O space can only be mapped to
external devices. The TrailBlazer’s internal SRAM has two
32KB regions that are restricted to either
DS
or
PS
space.
Register 0 controls the decoding for the internal SRAM.
Registers 1 through 5 control the address decoding for the
external devices on the Secondary Bus. For processors
that have A15 as the MSB, the three memory
spaces are restricted to 64KB each. However, the registers
do allow for programmable address ranges in 8KB blocks.
For processors with A[21:16] as the MSB, there is a 4MB
maximum address space that can be partitioned by
programming Registers 1 to 5.
Chip Selects (
CSMEM
x) are used to select external devices
on the Secondary Bus. These signals are generated by
combinations of the Memory Space signals and Addresses
Ap[13:21].
Strobes (
MSTRB
and
IOSTRB
) validate Memory Space
selections.
PS
and
DS
have to be validated by the assertion
of
MSTRB
and
IS
has to be validated by the assertion of
IOSTRB
.
The following provides detailed technical information
related to the pins on the device. For ease of reference, the
pin information is presented in a table format arranged both
by pin numbers and by pin names. A pin diagram has also
been included to be used as a visual point of reference.
Conventions
Table 1 details conventions that are used to present
information on the pins.
Table 1. Pin Conventions
Convention
NC
Meaning
This pin is reserved for ISSI, Inc. and must
be left as a 'No Connect'
Input-only
Output-only
Input or Output (Bi-directional)
Power pin
Ground pin
Active (or asserted) state occurs when pin
is at a low voltage
Multiplexed or Dual functionality
I
O
I/O
Power
Ground
SIGNAL
/
Pin Diagram
Refer to Figure 3 and Table 2 for the pin diagram for the
TrailBlazer device. It depicts the pin names and the
corresponding ball location. Pins marked as 'NC' are not
available and are defined as 'No Connect' pins. For more
detailed information on the pins refer to Table 5.
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