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參數(shù)資料
| 型號(hào)： | IS82C600 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 64K x 16 High-Speed SRAM with Address Decoding and Ready Logic(帶地址譯碼器和預(yù)備邏輯的高速靜態(tài)RAM) |
| 中文描述： | 64K的× 16高速的地址譯碼和就緒邏輯（帶地址譯碼器和預(yù)備邏輯的高速靜態(tài)RAM的靜態(tài)存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 1/21頁(yè) |
| 文件大?。?/td> | 129K |
| 代理商： | IS82C600 |
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IS82C600
IS82C600
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY
TB001-0B
01/20/99
1
This document contains PRELIMINARY DATA. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product.
We assume no responsibility for any errors which may appear in this publication. Copyright 1999, Integrated Silicon Solution, Inc.
TRAILBLAZER
High-Speed SRAM with
Address Decoding and Ready Logic
FEATURES
Zero wait-state performance on the Primary
Bus
— Point-to-point interface between the SRAM
and the high-speed processor
Seamless interface to Texas Instruments’
TMS320LC54x high-speed processor
Integrates the single-ported SRAM with a dual-
ported interface and handshake
— 9 ns access time to the SRAM
— Can also be used as a standalone, high-
speed SRAM
Integrates the port-to-port bridge function
— Broadcasts all processor cycles from
Primary Bus to the Secondary Bus
— Programmability to only broadcast
non-SRAM cycles to the Secondary Bus
— Supports older, slower peripheral devices on
the Secondary Bus
— Allows the processor transparent access to
the devices on the Secondary Bus through
XCVR
pin
— Supports a Boot ROM on the Secondary Bus
GENERAL DESCRIPTION
The IS82C600 TrailBlazer simplifies high-speed system
design and layout, providing an SRAM with zero wait-state
performance up to 90 MHz, address coding, and “Ready”
logic. In many cases, TrailBlazer allows existing system
designs to be easily upgraded, enabling the re-use of
already available ASICs and glue logic.
A key benefit of the TrailBlazer device is its ability to relieve
high-performance processors from a necessity to drive
heavily loaded multidrop buses by providing a point-to-
Features Address Decoding and Ready Logic
— A total of six Chip Selects
— Supports “Ready” logic signal generation for
memory and I/O
— Eliminates PALs for address decoding and
ready logic
— No “glue logic” interface for local peripherals
on the Secondary Bus processor
Allows dynamic re-allocation of memory spaces
for transparent block moves
— Programmable memory decoding allows
memory blocks to be accessed as either
Program Space (
PS
) or Data Space (
DS
)
— Programmable registers to map the internal
SRAM memory and external secondary port
devices into Data Space (
DS
), Program
Space (
PS
) and I/O Space (
IS
)
Can also be used as a standalone, high-speed
SRAM
Allows the shadowing of the ROM on the
Secondary Bus into the on-board SRAM
point, low-load interconnect to the high-speed memory
and buffering of the slower speed devices. This could allow
the processors to operate at a maximum frequency with
zero wait-states. Also, it eases PCB timing and layout-
related considerations, often allowing a reduction in the
number of PC board layers and the lowering of noise.
Programmable decodes and "Ready" generation logic
built into the TrailBlazer eliminates the need for expensive
PALs, other glue logic, and additional board space.
PRELIMINARY
JANUARY 1999
ISSI
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