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參數(shù)資料
| 型號(hào)： | IS82C600 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 64K x 16 High-Speed SRAM with Address Decoding and Ready Logic(帶地址譯碼器和預(yù)備邏輯的高速靜態(tài)RAM) |
| 中文描述： | 64K的× 16高速的地址譯碼和就緒邏輯（帶地址譯碼器和預(yù)備邏輯的高速靜態(tài)RAM的靜態(tài)存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 18/21頁(yè) |
| 文件大?。?/td> | 129K |
| 代理商： | IS82C600 |
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18
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY
TB001-0B
01/20/99
IS82C600
ISSI
Primary Bus Master Local Mode
T#
T12
Parameter
MSTRBp
/
IOSTRBp
Active to
OEMEMp
Active Delay
WEp
Active to
WMEMp
Active Delay
MSTRBp
/
IOSTRBp
Active to
WEMEMp
Delay
PSp
/
DSp
/
ISp
Active to
CSMEMp
[5:0] Delay
Min Max
0
Min Max
0
Min Max
0
Units
ns
5
5.5
6
T13
T14
T15
0
0
0
5
5
5
0
0
0
5.5
5.5
5.5
0
0
0
6
6
6
ns
ns
ns
Primary Bus Master Remote Mode (Non-
XCVR
Mode)
T#
T16
Parameter
R/
W
p,
PSp
,
DSp
,
ISp
,
MSTRBp
,
IOSTRBp
,
RDp
,
WEp
Delay to corresponding control signals on
Secondary Bus
Dp to Ds Write Mode (R/
W
=0)
Ds to Dp Read Mode (R/
W
=1)
MSTRBp
/
IOSTRBp
Active to
OEMEMs
Active Delay 0
WEp
Active to
WEMEMs
Active Delay
MSTRB
/
IOSTRBp
Active to
WEMEMs
Delay
PSp
/
DSp
/
ISp
Active to
CSMEMs
[5:0] Delay
Min Max
0
Min Max
0
Min Max
0
Units
ns
5
5.5
6
T17
T18
T19
T20
T21
T22
0
0
5
5
5
5
5
5
0
0
0
0
0
0
5.5
5.5
5.5
5.5
5.5
5.5
0
0
0
0
0
0
6
6
6
6
6
6
ns
ns
ns
ns
ns
ns
0
0
0
Primary Bus Master
XCVR
Mode
T#
T23
Parameter
R/
W
p,
PSp
,
DSp
,
ISp
,
MSTRBp
,
IOSTRBp
,
RDp
,
WEp
Delay to corresponding control signals on
Secondary Bus
Ds to Dp Delay (R/
W
=HIGH) Read
from Secondary Bus
Dp to Ds Delay (R/
W
=0) Write to Secondary Bus
Min Max
0
Min Max
0
Min Max
0
Units
ns
3
3
3
T24
0
5
0
5.5
0
6
ns
T25
0
5
0
5.5
0
6
ns
Note:
1. In the above list, the timing parameters are specified with the Primary Bus Master as the basis.
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