參數(shù)資料
型號(hào): IS82C600
廠商: Integrated Silicon Solution, Inc.
英文描述: 64K x 16 High-Speed SRAM with Address Decoding and Ready Logic(帶地址譯碼器和預(yù)備邏輯的高速靜態(tài)RAM)
中文描述: 64K的× 16高速的地址譯碼和就緒邏輯(帶地址譯碼器和預(yù)備邏輯的高速靜態(tài)RAM的靜態(tài)存儲(chǔ)器)
文件頁(yè)數(shù): 2/21頁(yè)
文件大?。?/td> 129K
代理商: IS82C600
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY
TB001-0B
01/20/99
IS82C600
ISSI
Figure 1. TrailBlazer Functional Block Diagram
PRODUCT OVERVIEW
The IS82C600 TrailBlazer integrates a high-speed 64K x
16 SRAM with a processor port-to-processor port bridge
function. This simplifies any high-speed designs by
providing a fast access time for the processor on the
Primary Port and enabling for a low-cost implementation of
a high-frequency system.
TrailBlazer combines a high-performance memory array,
programmable decodes, and "Ready" logic to achieve
maximum performance and flexibility, while keeping costs
at a minimum. In order to simplify system development,
TrailBlazer duplicates the Primary Bus signals on its
Secondary Bus to permit the use of existing system
components and ASICs together with a new generation of
high-performance processors.
On its Primary Bus, the TrailBlazer provides a high-speed
SRAM interface and then broadcasts the Primary Bus
cycles to its Secondary Bus, allowing the processor on its
Primary Bus to access peripherals on its Secondary Bus.
In many cases, since the peripherals are accessed by the
same signals, existing ASICs can be re-used.
TrailBlazer provides an optimized, seamless interface to
TI TMS320LC54x high-speed processor without the need
for any glue logic interfaces for local peripherals on the
Secondary Bus. TrailBlazer can also be used as shared
Local or Global Memory for a dual processor-based system
where the Chip Select logic on each bus allows for the
same data to be accessed at different locations in memory,
if so desired.
DECODER
SRAM
64K x 16
BUS
REPEATER
R/Wp
MSTRBp
Dp[15:0]
Ap[15:0]
Ds[15:0]
As[15:0]
CSINTp
Ap[21:16]
RDY
CLK
PRGM
XCVR
CSINTs
CSMEMs[5:0]
WEMEMs
OEMEMs
MSTRBs
PSp
DSp
ISp
HOLDAp
IOSTRBp
WEs
PSs
DSs
ISs
R/Ws
HOLDAs
IOSTRBs
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