參數(shù)資料
型號(hào)： INTEL82802AB
廠商： Intel Corp.
英文描述： Firmware Hub (FWH)
中文描述： 固件集線器（固件樞紐）
文件頁(yè)數(shù)： 49/53頁(yè)
文件大小： 471K
代理商： INTEL82802AB
Intel
82802AB/AC Firmware Hub
R
Datasheet
49
6.4.1.
Reset Operations
#
Symbol
Parameter
Notes
Min.
Max.
Unit
P1
t
PLPH
RST# pulse low time (If RST# is tied to V
CC
, this
specification is not applicable.)
100
ns
P2
t
PLRH
RST# low to reset during block erase or program
1, 2
20
μs
Note:
1. If RST# is asserted when the WSM is not busy (RY/BY# = ‘1’), the reset will complete within 100
ns.
2. A reset time, t
PHAV
, is required from the latter of RY/BY# or RST# going high until outputs are
valid.
6.4.2.
AC Waveforms for Reset Operations
IH
V
IL
V
RST# (P)
IH
V
IL
V
RY/BY# (R)
P1
P2
6.4.3.
A/A Mux Read-Only Operations
(1,3)
#
Symbol
Parameter
Notes
Min.
Max.
Unit
R1
t
AVAV
Read cycle time
250
ns
R2
t
AVCL
Row address setup to R/C# low
50
ns
R3
t
CLAX
Row address hold from R/C# low
50
ns
R4
t
AVCH
Column address setup to R/C# high
50
ns
R5
t
CHAX
Column address hold from R/C# high
50
ns
R6
t
CHQV
R/C# high to output delay
2
150
ns
R7
t
GLQV
OE# low to output delay
2
50
ns
R8
t
PHAV
RST# high to row address setup
1
μ
s
R9
t
GLQX
OE# low to output in low Z
0
ns
R10
t
GHQZ
OE# high to output in high Z
50
ns
R11
t
QXGH
Output hold from OE# high
0
ns
Note:
1. See the AC input/output reference waveform for the maximum allowable input slew rate.
2. OE# may be delayed up to t
CHQV
– t
GLQV
after the rising edge of R/C# without affecting t
CHQV
.
3. Tc = 0 °C to + 85 °C, 3.3 V ± 0.3 V V
CC
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