參數(shù)資料
型號： INTEL82802AB
廠商： Intel Corp.
英文描述： Firmware Hub (FWH)
中文描述： 固件集線器（固件樞紐）
文件頁數(shù)： 10/53頁
文件大小： 471K
代理商： INTEL82802AB
Intel
82802AB/AC Firmware Hub
R
10
Datasheet
1.1.1.
Intel Firmware Hub Interface
The Intel Firmware Hub (Intel FWH) interface consists primarily of a 5-signal communication interface
used to control the operation of the device in a system environment. The buffers for this interface were
designed to be PCI compliant. To ensure the effective delivery of security and manageability features, the
Intel FWH interface is the only way access the full feature set of the device. The Intel FWH interface is
equipped to operate at 33 MHz, synchronous with the PCI bus.
1.1.2.
Address/Address-Multiplexed Interface
The A/A Mux refers to the multiplexed row and column addresses in this interface. This approach is
required so that the device can be tested and programmed quickly with automated test equipment (ATE)
or off-board PROM programmers in the OEM’s manufacturing flow. This interface also allows the
device to have an efficient programming interface with potentially large future densities, while still fitting
into a 32-pin package. Only basic reads, programming, and erasure of the nonvolatile memory blocks can
be performed through the A/A Mux interface. In this mode, the Intel FWH features, security features, and
registers are unavailable. A row/column (R/C#) pin determines which set of addresses (rows or columns)
is latched. See the A/A Mux pin description table for more information.
1.2.
Nonvolatile Flash Memory Core
The primary feature of the Intel FWH component is a nonvolatile memory core based on Intel
Flash
Technology. This high-performance memory array is arranged in eight (4-Mbit device) or sixteen (8-
Mbit device) 64-KB blocks.
Intel
Flash Technology enables fast factory programming and low-power designs. Specifically designed
for 3-V systems, this component supports read operations at 3.3 V V
CC
and block erase and program
operations at 3.3 V and 12 V V
PP
. The 12 V V
PP
option yields the fastest program performance, which
will increase factory throughput, but is not recommended for standard in-system FWH operation in the
platform, due to an
80-hr limit for 12 V
on the V
PP
pin over the lifetime of the device, whether or not
programming is taking place. With the 3.3-V V
PP
option (recommended for in-system operation), V
CC
and V
PP
may be tied together for a simple, low-power 3-V design. In addition to the voltage flexibility,
the dedicated V
PP
pin provides complete data protection when V
PP
≤
V
PPLK
. Internal V
PP
detection
circuitry automatically configures the device for block erase and program operations. While current for
12-V programming will be drawn from V
PP
, 3.3-V programming solutions should design their board such
that V
PP
draws from the same supply as V
CC
, and should assume that full programming current may be
drawn from either pin.
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