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參數(shù)資料
| 型號(hào)： | INTEL82802AB |
| 廠商： | Intel Corp. |
| 英文描述： | Firmware Hub (FWH) |
| 中文描述： | 固件集線器（固件樞紐） |
| 文件頁數(shù)： | 26/53頁 |
| 文件大?。?/td> | 471K |
| 代理商： | INTEL82802AB |
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Intel
82802AB/AC Firmware Hub
R
26
Datasheet
Write Lock
The default write status of all blocks upon power-up is write-locked. Any program or erase operations
attempted on a locked block will return an error in the status register (indicating block lock). The status
of the locked block can be changed to unlocked by clearing the write-lock bit, provided the lock-down
bit also is not set. The current write-lock status of a particular block can be determined by reading the
corresponding write-lock bit. The write-lock functions in conjunction with the hardware write-lock pins,
TBL# and WP#. When active, these pins take precedence over the register locking function and write-
lock the top block or remaining blocks, respectively. Reading this register will not read the state of the
TBL# or WP# pin.
Read Lock
The default read status of all blocks upon power-up is read-unlocked. When a block’s read-lock bit is set,
data cannot be read from that block. An attempted read from a read-locked block will result in the data
00h. (Note that failure is not reflected in the status register.) The read-lock status can be unlocked by
clearing the read-lock bit, provided the lock-down bit has not been set. The current read-lock status of a
particular block can be determined by reading the corresponding read-lock bit.
Lock-Down
In the Intel FWH interface mode, the default lock-down status of all blocks upon power-up is not-locked-
down. The lock-down bit for any block may be set, but only once, because future attempts to change that
block-locking register will be ignored. The lock-down bit is cleared only upon a device reset with RST#
or INIT#. The current lock-down status of a particular block can be determined by reading the
corresponding lock-down bit. Once a block’s lock-down bit is set, the read- and write-lock bits for that
block can no longer be modified, and the block is locked-down in its current state of read and write
accessibility.
4.9.2.
General-Purpose Input Register
This register reads the status of the FGPI [4:0] pins on the Intel FWH. Since this is a pass-through
register, there is no default value, only the state of the pins at power-up.
4.9.2.1.
GPI_REG — General-Purpose Input Register
Memory Address:
Default Value:
Access:
Size:
FFBC0100h
N/A
R0
8 bits
Bit
Function
7:5
Reserved
4
FGPI[4].
Reads status of general-purpose input pin (PLCC-30/TSOP-7).
3
FGPI[3].
Reads status of general-purpose input pin (PLCC-3/TSOP-15).
2
FGPI[2].
Reads status of general-purpose input pin (PLCC-4/TSOP-16).
1
FGPI[1].
Reads status of general-purpose input pin (PLCC-5/TSOP-17).
0
FGPI[0].
Reads status of general-purpose input pin (PLCC-6/TSOP-18).
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