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參數(shù)資料
| 型號： | INTEL82802AB |
| 廠商： | Intel Corp. |
| 英文描述： | Firmware Hub (FWH) |
| 中文描述： | 固件集線器（固件樞紐） |
| 文件頁數(shù)： | 41/53頁 |
| 文件大?。?/td> | 471K |
| 代理商： | INTEL82802AB |
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Intel
82802AB/AC Firmware Hub
R
Datasheet
41
Table 16.
FWH Read Cycle
Clock
Cycle
Field
Name
Field Contents
1
FWH[3:0]
FWH[3:0]
Direction
Comments
1
START
1101
IN
FWH4 must be active (low) for the part to respond.
Only the last start field (before FWH4 transitioning high)
should be recognized. The START field contents
indicate an FWH memory read cycle.
2
IDSEL
0000
to
1111
IN
Indicates which FWH device should respond. If the
IDSEL (ID select) field matches the value ID[3:0], then
that particular device will respond to subsequent
commands.
3-9
IMADDR
YYYY
IN
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most-significant nibble first.
On multibyte data transfers, lower-order addresses will
be zero, depending on page size.
10
IMSIZE
0000 (1 byte)
IN
A field of this size indicates how many bytes will be
transferred during multibyte operations. The FWH will
only support single-byte transfers.
11
TAR0
1111
IN
then float
In this clock cycle, the master (Intel ICH) has driven the
bus to all 1s and then floats the bus, prior to the next
clock cycle. This is the first part of the bus “turnaround
cycle.”
12
TAR1
1111 (float)
Float then
OUT
The FWH takes control of the bus during this cycle.
During the next clock cycle, it will be driving “sync
data.”
13-14
WSYNC
0101 (WAIT)
OUT
The FWH outputs the value 0101, a wait-sync
(WSYNC, a.k.a. “short-sync”), for two clock cycles. This
value indicates to the master (Intel ICH) that data is not
yet available from the part. This number of wait-syncs
is a function of the device’s access time.
15
RSYNC
0000 (READY)
OUT
During this clock cycle, the FWH will generate a “ready-
sync” (RSYNC) indicating that the least-significant
nibble of the least-significant byte will be available
during the next clock cycle.
16
DATA
YYYY
OUT
YYYY is the least-significant nibble of the least-
significant data byte.
17
DATA
YYYY
OUT
YYYY is the most-significant nibble of the least-
significant data byte.
17+
3 x 2
+
2
n
“DATA”
2 WSYNCS +
1 RSYNC +
2 DATA
OUT
n = IMSIZE. Each subsequent byte of data requires 2
wait-syncs + 1 ready-sync + 2 data nibbles.
The FWH supports only n=0000 (single-byte) reads.
Previous
+ 1
TAR0
1111
OUT
then float
In this clock cycle, the Inel FWH has driven the bus to
all ones and then floats the bus prior to the next clock
cycle. This is the first part of the bus “turnaround cycle.”
Previous
+ 1
TAR1
1111 (float)
Float then
IN
The master (Intel ICH) resumes control of the bus
during this cycle.
Note:
1. Field contents are valid on the rising edge of the present clock cycle.
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