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| 型號： | INTEL740 |
| 英文描述： | 64-Bit Graphics (GUI) Accelerator |
| 中文描述： | 64位圖形（GUI）的加速器 |
| 文件頁數(shù)： | 24/41頁 |
| 文件大小： | 435K |
| 代理商： | INTEL740 |
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Intel387
TM
DX MATH COPROCESSOR
Table 3.4. Bus Cycles Definition
STEN
NPS1
Y
NPS2
CMD0
Y
W/R
Y
Bus Cycle Type
0
x
x
x
x
MCP not selected and all
outputs in floating state
MCP not selected
MCP not selected
CW or SW read from MCP
Opcode write to MCP
Data read from MCP
Data write to MCP
1
1
1
1
1
1
1
x
0
0
0
0
x
0
1
1
1
1
x
x
0
0
1
1
x
x
0
1
0
1
communication protocol makes possible high-speed
transfer of opcodes and operands between the In-
tel386 DX CPU and Intel387 DX MCP. The Intel387
DX MCP is designed so that no additional compo-
nents are required for interface with the Intel386 DX
CPU. The Intel387 DX MCP shares the 32-bit wide
local bus of the Intel386 DX CPU and most control
pins of the Intel387 DX MCP are connected directly
to pins of the Intel386 DX Microprocessor.
3.3.1 BUS CYCLE TRACKING
The ADS
Y
and READY
Y
signals allow the MCP to
track the beginning and end of the Intel386 DX CPU
bus cycles, respectively. When ADS
Y
is asserted at
the same time as the MCP chip-select inputs, the
bus cycle is intended for the MCP. To signal the end
of a bus cycle for the MCP, READY
Y
may be assert-
ed directly or indirectly by the MCP or by other bus-
control logic. Refer to Table 3.4 for definition of the
types of MCP bus cycles.
3.3.2 MCP ADDRESSING
The NPS1
Y
, NPS2 and STEN signals allow the
MCP to identify which bus cycles are intended for
the MCP. The MCP responds only to I/O cycles
when bit 31 of the I/O address is set. In other words,
the MCP acts as an I/O device in a reserved I/O
address space.
Because A
31
is used to select the MCP for data
transfers, it is not possible for a program running on
the Intel386 DX CPU to address the MCP with an I/
O instruction. Only ESC instructions cause the In-
tel386 DX Microprocessor to communicate with the
MCP. The Intel386 DX CPU BS16
Y
input must be
inactive during I/O cycles when A
31
is active.
3.3.3 FUNCTION SELECT
The CMD0
Y
and W/R
Y
signals identify the four
kinds of bus cycle: control or status register read,
data read, opcode write, data write.
3.3.4 CPU/MCP Synchronization
The pin pairs BUSY
Y
, PEREQ, and ERROR
Y
are
used for various aspects of synchronization between
the CPU and the MCP.
BUSY
Y
is used to synchronize instruction transfer
from the Intel386 DX CPU to the MCP. When the
MCP recognizes an ESC instruction, it asserts
BUSY
Y
. For most ESC instructions, the Intel386 DX
CPU waits for the MCP to deassert BUSY
Y
before
sending the new opcode.
The MCP uses the PEREQ pin of the Intel386 DX
CPU to signal that the MCP is ready for data transfer
to or from its data FIFO. The MCP does not directly
access memory; rather, the Intel386 DX Microproc-
essor provides memory access services for the
MCP. Thus, memory access on behalf of the MCP
always obeys the rules applicable to the mode of the
Intel386 DX CPU, whether the Intel386 DX CPU be
in real-address mode or protected mode.
Once the Intel386 DX CPU initiates an MCP instruc-
tion that has operands, the Intel386 DX CPU waits
for PEREQ signals that indicate when the MCP is
ready for operand transfer. Once all operands have
been transferred (or if the instruction has no oper-
ands) the Intel386 DX CPU continues program exe-
cution while the MCP executes the ESC instruction.
In 8086/8087 systems, WAIT instructions may be
required to achieve synchronization of both com-
mands and operands. In 80286/80287, Intel386 DX
Microprocessor and Intel387 DX Math Coprocessor
systems, WAIT instructions are required only for op-
erand synchronization; namely, after MCP stores to
memory (except FSTSW and FSTCW) or loads from
memory. Used this way, WAIT ensures that the val-
ue has already been written or read by the MCP be-
fore the CPU reads or changes the value.
24
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