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| 型號： | INTEL740 |
| 英文描述： | 64-Bit Graphics (GUI) Accelerator |
| 中文描述： | 64位圖形（GUI）的加速器 |
| 文件頁數(shù)： | 22/41頁 |
| 文件大?。?/td> | 435K |
| 代理商： | INTEL740 |
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Intel387
TM
DX MATH COPROCESSOR
3.1.11 BUS READY INPUT (READY
Y
)
This input indicates to the MCP when a Intel386 DX
CPU bus cycle is to be terminated. It is used by the
bus-control logic to trace bus activities. Bus cycles
can be extended indefinitely until terminated by
READY
Y
. This input should be connected to the
same signal that drives the Intel386 DX CPU
READY
Y
input. Setup and hold times are refer-
enced to CPUCLK2.
3.1.12 READY OUTPUT (READYO
Y
)
This pin is activated at such a time that write cycles
are terminated after two clocks (except FLDENV
and FRSTOR) and read cycles after three clocks. In
configurations where no extra wait states are re-
quired, this pin must directly or indirectly drive the
Intel386 DX CPU READY
Y
input. Refer to section
3.4 ‘‘Bus Operation’’ for details. This pin is activated
only during bus cycles that select the MCP. This sig-
nal is referenced to CPUCLK2.
3.1.13 STATUS ENABLE (STEN)
This pin serves as a chip select for the MCP. When
inactive, this pin forces BUSY
Y
, PEREQ, ERROR
Y
,
and READYO
Y
outputs into floating state. D31–D0
are normally floating and leave floating state only if
STEN is active and additional conditions are met.
STEN also causes the chip to recognize its other
chip-select inputs. STEN makes it easier to do on-
board testing (using the overdrive method) of other
chips in systems containing the MCP. STEN should
be pulled up with a resistor so that it can be pulled
down when testing. In boards that do not use on-
board testing, STEN should be connected to V
CC
.
Setup and hold times are relative to CPUCLK2. Note
that STEN must maintain the same setup and hold
times as NPS1
Y
, NPS2, and CMD0
Y
(i.e. if STEN
changes state during a Intel387 DX MCP bus cycle,
it should change state during the same CLK period
as the NPS1
Y
, NPS2, and CMD0
Y
signals).
3.1.14 MCP Select
Y
1 (NPS1
Y
)
When active (along with STEN and NPS2) in the first
period of a Intel386 DX CPU bus cycle, this signal
indicates that the purpose of the bus cycle is to com-
municate with the MCP. This pin should be connect-
ed directly to the Intel386 DX CPU M/IO
Y
pin, so
that the MCP is selected only when the Intel386 DX
CPU performs I/O cycles. Setup and hold times are
referenced to CPUCLK2.
3.1.15 MCP SELECT
Y
2 (NPS2)
When active (along with STEN and NPS1
Y
) in the
first period of an Intel386 DX CPU bus cycle, this
signal indicates that the purpose of the bus cycle is
to communicate with the MCP. This pin should be
connected directly to the Intel386 DX CPU A31 pin,
so that the MCP is selected only when the Intel386
DX CPU uses one of the I/O addresses reserved for
the MCP (800000F8 or 800000FC). Setup and hold
times are referenced to CPUCLK2.
3.1.16 COMMAND (CMD0
Y
)
During a write cycle, this signal indicates whether an
opcode (CMD0
Y
active) or data (CMD0
Y
inactive)
is being sent to the MCP. During a read cycle, it
indicates whether the control or status register
(CMD0
Y
active) or a data register (CMD0
Y
inactive)
is being read. CMD0
Y
should be connected directly
to the A2 output of the Intel386 DX Microprocessor.
Setup and hold times are referenced to CPUCLK2.
3.2 Processor Architecture
As shown by the block diagram on the front page,
the MCP is internally divided into three sections: the
bus control logic (BCL), the data interface and con-
trol unit, and the floating point unit (FPU). The FPU
(with the support of the control unit which contains
the sequencer and other support units) executes all
numerics instructions. The data interface and control
unit is responsible for the data flow to and from the
FPU and the control registers, for receiving the in-
structions, decoding them, and sequencing the mi-
croinstructions, and for handling some of the admin-
istrative instructions. The BCL is responsible for the
Intel386 DX CPU bus tracking and interface. The
BCL is the only unit in the Intel387 DX MCP that
must run synchronously with the Intel386 DX CPU;
the rest of the MCP can run asynchronously with
respect to the Intel386 DX Microprocessor.
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