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參數(shù)資料
| 型號： | INTEL740 |
| 英文描述： | 64-Bit Graphics (GUI) Accelerator |
| 中文描述： | 64位圖形（GUI）的加速器 |
| 文件頁數(shù)： | 15/41頁 |
| 文件大小： | 435K |
| 代理商： | INTEL740 |
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Intel387
TM
DX MATH COPROCESSOR
Table 2.6. Intel386
TM
DX Microprocessor Interrupt Vectors Reserved for MCP
Interrupt
Number
Cause of Interrupt
7
An ESC instruction was encountered when EM or TS of the Intel386
TM
DX CPU control
register zero (CR0) was set. EM
e
1 indicates that software emulation of the instruction is
required. When TS is set, either an ESC or WAIT instruction causes interrupt 7. This
indicates that the current MCP context may not belong to the current task.
9
An operand of a coprocessor instruction wrapped around an addressing limit (0FFFFH for
small segments, 0FFFFFFFFH for big segments, zero for expand-down segments) and
spanned inaccessible addresses
(1)
. The failing numerics instruction is not restartable. The
address of the failing numerics instruction and data operand may be lost; an FSTENV does
not return reliable addresses. As with the 80286/80287, the segment overrun exception
should be handled by executing an FNINIT instruction (i.e. an FINIT without a preceding
WAIT). The return address on the stack does not necessarily point to the failing instruction
nor to the following instruction. The interrupt can be avoided by never allowing numeric
data to start within 108 bytes of the end of a segment.
13
The first word or doubleword of a numeric operand is not entirely within the limit of its
segment. The return address pushed onto the stack of the exception handler points at the
ESC instruction that caused the exception, including any prefixes. The Intel387
TM
DX MCP
has not executed this instruction; the instruction pointer and data pointer register refer to a
previous, correctly executed instruction.
16
The previous numerics instruction caused an unmasked exception. The address of the
faulty instruction and the address of its operand are stored in the instruction pointer and
data pointer registers. Only ESC and WAIT instructions can cause this interrupt. The
Intel386
TM
DX CPU return address pushed onto the stack of the exception handler points
to a WAIT or ESC instruction (including prefixes). This instruction can be restarted after
clearing the exception condition in the MCP. FNINIT, FNCLEX, FNSTSW, FNSTENV, and
FNSAVE cannot cause this interrupt.
1.
An operand may wrap around an addressing limit when the segment limit is near an addressing limit and the operand is near the largest valid
address in the segment. Because of the wrap-around, the beginning and ending addresses of such an operand will be at opposite ends of the
segment. There are two ways that such an operand may also span inaccessible addresses: 1) if the segment limit is not equal to the addressing
limit (e.g. addressing limit is FFFFH and segment limit is FFFDH) the operand will span addresses that are not within the segment (e.g. an 8-byte
operand that starts at valid offset FFFC will span addresses FFFC–FFFF and 0000-0003; however addresses FFFE and FFFF are not valid,
because they exceed the limit); 2) if the operand begins and ends in present and accessible pages but intermediate bytes of the operand fall in a
not-present page or a page to which the procedure does not have access rights.
2.5 Exception Handling
The Intel387 DX MCP detects six different exception
conditions that can occur during instruction execu-
tion. Table 2.7 lists the exception conditions in order
of precedence, showing for each the cause and the
default action taken by the MCP if the exception is
masked by its corresponding mask bit in the control
word.
Any exception that is not masked by the control
word sets the corresponding exception flag of the
status word, sets the ES bit of the status word, and
asserts the ERROR
Y
signal. When the CPU at-
tempts to execute another ESC instruction or WAIT,
exception 7 occurs. The exception condition must
be resolved via an interrupt service routine. The In-
tel386 DX Microprocessor saves the address of the
floating-point instruction that caused the excep-
tion and the address of any memory operand re-
quired by that instruction.
2.6 Initialization
Intel387 DX MCP initialization software must exe-
cute an FNINIT instruction (i.e. an FINIT without a
preceding WAIT)toclearERROR
Y
.Afterahardware
RESET, the ERROR
Y
output is asserted to indicate
that a Intel387 DX MCP is present. To accomplish
this, the IE and ES bits of the status word are set,
and the IM bit in the control word is reset. After
FNINIT, the status word and the control word have
the same values as in an 80287 after RESET.
15
15
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