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| 型號： | INSTRUCTIN603EWP |
| 英文描述： | Optimizing the Instruction Execution on the 603e |
| 中文描述： | 優(yōu)化了603e的指令執(zhí)行 |
| 文件頁數(shù)： | 48/54頁 |
| 文件大?。?/td> | 325K |
| 代理商： | INSTRUCTIN603EWP |
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RISC Microprocessor Division
Page 48
Accessing misaligned addresses can result in significant performance penalties in most RISC
superscalar microarchitectures.
On the 603e, a data address is aligned if it falls on a multiple of the access size. Thus a word (4-byte)
access is aligned at 0x0000 and 0x0004 but not at 0x0002; a doubleword (8-byte) access is aligned at
0x0000 and 0x0008 but not at 0x0004.
If the data address of a load or store in the LSU EA slot is not aligned, then it is split into two aligned
accesses.
Figure 1
shows a misaligned store. A is first split into the aligned store A1, then on the next
clock it is split into the aligned store A2 and the LSU EA entry removed. In
Figure 2
we have a
misaligned load, in which A is split into aligned loads A1 and A2. Note that because the load stayed in
the LSU EA slot for more than one cycle, it remains in this slot until its data comes back (see LSU EA
stall above).
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