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RISC Microprocessor Division
Page 44
Superscalar architectures frequently signal between different parts of the architecture, in order to
coordinate various aspects of the units. Diagrams may not always show all the signals that are shared
between units with the system. These interactions can also cause stalls. We discuss a case in which
the state of the completion queue can affect instruction flow in the LSU.
Since the 603e allows out-of-order execution, instructions will frequently dispatch to the LSU (as well as
other execution units) before previous instructions have finished executing. If one of these previous
instructions generates an exception, then all subsequent instructions (including the LSU instruction)
must be canceled from the instruction flow (
flushed
). Various parts of the processor, including the
LSU, must be careful to stall instructions that could be canceled before they permanently change the
processor state.
On the 603e, if a load or store’s entry in the completion queue is not in the bottom slot, then there are
preceding instructions that could potentially generate exceptions which may cancel the load or store.
The instruction must be stalled before it reaches a state that cannot be canceled.
Figures 1-2
depict this situation, in which instruction A is stalled because its entry in the completion
queue is not in the bottom slot. In
Figure 1
, store A is stalled in the second slot of the LSU store
queue, since writing to the data cache would incur too much of a penalty to undo.
In
Figure 2
, load A is stalled in the data cache miss slot if it is accessing guarded memory.
Guarded
memory
is typically used to prevent out-of-order loads to I/O devices, which may produce undesired
results otherwise. Note that even if load A were at the bottom of the completion queue, the 603e would
stall the load for one cycle before making its request to the BIU.