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| 型號： | INSTRUCTIN603EWP |
| 英文描述： | Optimizing the Instruction Execution on the 603e |
| 中文描述： | 優(yōu)化了603e的指令執(zhí)行 |
| 文件頁數(shù)： | 31/54頁 |
| 文件大?。?/td> | 325K |
| 代理商： | INSTRUCTIN603EWP |
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RISC Microprocessor Division
Page 31
As previously mentioned, the Normalizer stage can take multiple cycles, thereby stalling the flow of
instructions within the FPU. When FP instructions occupy the Normalizer, Multiplier, and Adder stages
at the same time, a signal will be sent to the dispatcher, halting dispatch of instructions to the floating-
point unit. Even if normalization doesn’t stall the pipeline, the distance between the Normalizer and
dispatcher prevents the FPU from informing the dispatcher to resume dispatching until after it is too late
to dispatch an instruction on that clock. This causes a stall after every third consecutive single cycle
FP instruction.
The wait stage that exists after the normalization stage also contributes to potential stalls. The
additional wait stage causes FPR rename registers to be released one cycle after the FP operation is
complete. This causes a stall if a series of single-cycle FP instructions are executing in the FPU. After
every fourth single cycle FP instruction, a stall will occur due to lack of FPR rename registers.
These two stall scenarios cause a series of single-cycle FP instructions to dispatch in clocks 1, 2, 3, 5,
7, 8, 9, 11, 13, 14, 15, etc. The next slide depicts the stall scenarios described above.
Finally, if exception checking is enabled in the FPU, the instruction may have to wait in the Normalizer
while exceptions are checked. One can enhance performance by pre-qualifying data prior to running it
and polling for possible exceptions at the last reasonable instant.
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