RISC Microprocessor Division
Page 3
This presentation discusses techniques for optimizing instruction execution in a superscalar
microprocessor architecture such as the PowerPC 603e microprocessor.
Instruction execution in a superscalar processor is enhanced by allowing the parallel execution of
multiple instructions. In order to enable the maximum potential of most superscalar processors, one
needs to be aware of their instruction flow and execution mechanisms. Optimal performance in a
microprocessor can be attained by ensuring a continuous flow of instructions through the instruction
pipeline.
Being aware of the dependencies and constraints of the instruction flow mechanisms allows one to
generate code that can most effectively and optimally take advantage of all the capabilities of a
superscalar processor such as the PowerPC 603e microprocessor.
The 603e is a low-power implementation of the PowerPC family of reduced instruction set computer
(RISC) microprocessors. The 603e is a superscalar processor capable of issuing and retiring as many
as three instructions per clock. Instructions can “execute” out-of-order for increased performance, but
they “retire” in-order to ensure functional correctness and well-ordered behavior.
In this paper, we first discuss the instruction flow mechanism of the PowerPC 603e microprocessor and
then describe dependencies and constraints that should be avoided to reduce stalls in the instruction
pipeline and maximize performance.
By closely examining the instruction flow mechanism of the 603e, a software developer will not only be
able to optimize code for the 603e, but will also be able to understand some of the general principles
behind superscalar microprocessors that can impact performance.