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參數資料
| 型號： | INSTRUCTIN603EWP |
| 英文描述： | Optimizing the Instruction Execution on the 603e |
| 中文描述： | 優(yōu)化了603e的指令執(zhí)行 |
| 文件頁數： | 33/54頁 |
| 文件大?。?/td> | 325K |
| 代理商： | INSTRUCTIN603EWP |
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RISC Microprocessor Division
Page 33
Series of single-cycle FP instructions
Clock 0
: First two instructions (
A
and
B
) are brought into the instruction queue (IQ).
A
is marked for
dispatch.
Clock 1
:
A
is dispatched to the Multiplier stage of the FPU and is allocated FP rename register 0.
B
is
marked for dispatch.
C
and
D
are brought into the IQ.
Clock 2
:
A
steps to the Adder stage in the FPU.
B
is dispatched to the Multiplier stage and is
allocated FP rename register 1.
C
is marked for dispatch.
E
is brought into the IQ. (Anything after
E
is
ignored for this discussion.)
Clock 3
:
A
steps to the Normalizer stage in the FPU.
B
steps to the Adder stage.
C
is dispatched to
the Multiplier stage and is allocated FP rename register 2. At this point, a signal is sent to the
dispatcher indicating that no instruction may be dispatched to the FPU until a stage has been freed up.
This signal is negated as soon as the Normalizer stage is finished, but this will be too late to actually
permit an instruction to dispatch on the next clock.
D
, therefore, stalls in the IQ (is not marked for
dispatch).
Clock 4
:
A
steps to a wait stage in the FPU. A signal has been sent to the completion unit indicating
that
A
is finished and, since it is the oldest instruction in the completion queue, it is permitted to retire.
B
steps to the Normalizer stage.
C
steps to the Adder stage.
D
is given permission to dispatch on the
next clock.
Continued on next slide
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