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| 型號： | INSTRUCTIN603EWP |
| 英文描述： | Optimizing the Instruction Execution on the 603e |
| 中文描述： | 優(yōu)化了603e的指令執(zhí)行 |
| 文件頁數(shù)： | 36/54頁 |
| 文件大?。?/td> | 325K |
| 代理商： | INSTRUCTIN603EWP |
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RISC Microprocessor Division
Page 36
Completion of floating-point unit instructions is a potential source of stalls. Due to the single write-back
port on the floating point register file, multiple instructions trying to write back floating-point results will
have to do so in a sequential manner. This will typically happen in matrix math where math operations
occur in parallel with loads that initialize registers for subsequent math operations.
The code segment above depicts such a scenario. Adjacent load and fmadd instructions have no
register dependencies nor do they require the same execution unit. Therefore, each pair can dispatch
together, execute in parallel, and even finish (update rename registers) in parallel. However, due to the
single write back port, this code has an effective throughput of only a single instruction per clock. If this
code is part of a larger code segment that includes integer instructions, then it is possible to achieve a
greater instruction throughput by intermixing integer instructions (from elsewhere in the code sequence)
with these floating-point instructions. This will allow the integer execution and write-back to overlap
with the floating-point write-back, thereby improving the overall instruction throughput on the entire
code segment.
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