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參數(shù)資料
| 型號： | IMC016FLSG |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5 V Series 200 Flash Memory Card(5V系列200閃速存儲器插卡) |
| 中文描述： | 16M X 8 FLASH 5V PROM CARD, 200 ns, XMA68 |
| 封裝： | PC CARD |
| 文件頁數(shù)： | 33/35頁 |
| 文件大?。?/td> | 217K |
| 代理商： | IMC016FLSG |
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E
iMC008/016/024/032/048/064FLSG
33
PRELIMINARY
049105
Figure 7. Power-Up Timing for Systems Supporting RESET#
8.6
Block Erase, Write, and Lock-Bit Configuration Performance
(3,4)
Sym
Parameter
Notes
Min
Typ
(1)
Max
Units
t
WHQV1
t
EHQV1
t
WHQV2
t
EHQV2
Write Buffer Word Write Time
2, 5, 6
TBD
6
TBD
μs
Word Write Time
(Using Word Write Command)
Block Write Time
(Using Write to Buffer Command)
Block Erase Time
2, 6
TBD
180
TBD
μs
2, 6
TBD
0.8
TBD
sec
t
WHQV4
t
EHQV4
t
WHQV5
t
EHQV5
t
WHQV6
t
EHQV6
t
WHRH
t
EHRH
NOTES:
1.
2
TBD
0.7
TBD
sec
Set Lock-Bit Time
2
TBD
32
TBD
μs
Clear Block Lock-Bits Time
2
TBD
0.3
TBD
sec
Erase Suspend Latency Time to Read
26
35
μs
Typical values measured at T
= +25 °C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to
change based on device characterization.
Excludes system-level overhead.
These performance numbers are valid for all speed versions.
Sampled but not 100% tested.
These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary.
The maximum write time is the absolute maximum time it takes the write algorithm to complete. The overwhelming
majority of the bits are written within the typical value specified. To maximize system performance, the RDY/BSY# signal
should be polled to determine the completion of a write operation.
2.
3.
4.
5.
6.
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