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參數(shù)資料
| 型號(hào)： | IMC016FLSG |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5 V Series 200 Flash Memory Card(5V系列200閃速存儲(chǔ)器插卡) |
| 中文描述： | 16M X 8 FLASH 5V PROM CARD, 200 ns, XMA68 |
| 封裝： | PC CARD |
| 文件頁(yè)數(shù)： | 15/35頁(yè) |
| 文件大?。?/td> | 217K |
| 代理商： | IMC016FLSG |
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E
5.1.3
iMC008/016/024/032/048/064FLSG
15
PRELIMINARY
READ STATUS REGISTER
COMMAND
The status register may be read to determine when
a block erase, write, or lock-bit configuration
operation is complete and whether the operation
completed successfully. Table 6 defines the content
and format of the status register. The register may
be read at any time by writing the Read Status
Register command. After writing this command, all
subsequent read operations output data from the
status register until another valid command is
written. The status register contents are latched on
the falling edge of OE# or the first edge of CE
#
and CE
# that enables the device (see Table 3,
Card Signal Values for the Card’s Bus Operations
and Modes
). OE# must toggle to V
IH
or the device
enter standby mode (see Table 3) before further
reads to update the status register latch.
During a word write, write to buffer, block erase, set
lock-bit, or clear lock-bit command sequence, only
SR.7 is valid until the Write State Machine
completes or suspends the operation. Device I/O
pins DQ
0
–DQ
6
and DQ
8
–DQ
15
are placed in a high-
impedance state. When the operation completes or
suspends (check status register bit 7), all contents
of the status register are valid when read.
5.1.4
CLEAR STATUS REGISTER
COMMAND
Status register bits SR.5, SR.4, SR.3, and SR.1 are
set to “1”s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 6). By
allowing system software to reset these bits,
several operations (such as cumulatively erasing or
locking of multiple blocks or writing of several bytes
in sequence) may be performed. The status register
may be polled to determine if an error occurred
during the sequence.
To clear the status register, the Clear Status
Register command (50H) is written. The Clear
Status Register command is only valid when the
WSM is off or the device is suspended.
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