參數(shù)資料
型號(hào)： IMC016FLSG
廠商： INTEL CORP
元件分類： DRAM
英文描述： 5 V Series 200 Flash Memory Card(5V系列200閃速存儲(chǔ)器插卡)
中文描述： 16M X 8 FLASH 5V PROM CARD, 200 ns, XMA68
封裝： PC CARD
文件頁(yè)數(shù)： 32/35頁(yè)
文件大?。?/td> 217K
代理商： IMC016FLSG
iMC008/016/024/032/048/064FLSG
E
32
PRELIMINARY
8.5.3
POWER-UP TIMING
(1, 2)
Symbol
Parameter
Notes
Min
Max
Units
PCMCIA
V
i
(CE)
CE# Signal Level (0.0 V < V
CC
< 2.0 V)
1
0
V
iMAX
V
CE# Signal Level (2.0 V < V
CC
< V
IH
)
1
V
CC
– 0.1
V
iMAX
V
CE# Signal Level (V
IH
< V
CC
)
1
V
IH
V
iMAX
V
t
su
(V
CC
)
CE# Setup Time
20
ms
t
su
(RESET)
CE# Setup Time
20
ms
t
rec
(V
CC
)
CE# Recover Time
1.0
μs
t
pr
V
CC
Rising Time
2
0.1
300
ms
t
pf
V
CC
Falling Time
2
3.0
300
ms
t
w
(RESET)
RESET Width
10
μs
t
h
(Hi-Z RESET) RESET Width
3
36
μs
t
s
(Hi-Z RESET) RESET Width
0
ms
NOTES:
1.
2.
V
iMAX
means Absolute Maximum Voltage for input in the period of 0.0 V < V
CC
< 2.0 V, V
i
(CE#) is only 0.00 V ~ V
iMAX.
The t
and t
are defined as
“l(fā)inear waveforms” in the period of 10% to 90%, or vice-versa. Even if the waveform is not a
“l(fā)inear waveform,” its rising and falling time must meet this specification.
If RESET# is asserted while a block erase, write, or lock-bit configuration operation is not executing, then the minimum
required RESET# Pulse Low Time is 1 μs.
A rest time, t
PHQV
(reference Section 8.5.1) is required from BUSY# or RESET# going high until outputs are valid.
3.
4.
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