參數(shù)資料
型號(hào)： IMC016FLSG
廠商： INTEL CORP
元件分類： DRAM
英文描述： 5 V Series 200 Flash Memory Card(5V系列200閃速存儲(chǔ)器插卡)
中文描述： 16M X 8 FLASH 5V PROM CARD, 200 ns, XMA68
封裝： PC CARD
文件頁(yè)數(shù)： 20/35頁(yè)
文件大?。?/td> 217K
代理商： IMC016FLSG
iMC008/016/024/032/048/064FLSG
E
20
PRELIMINARY
5.2.1
BLOCK WRITE COMMAND
To write to the flash device write buffer, a Write to
Buffer command sequence is initiated. A variable
number of bytes, up to the buffer size, can be
loaded into the buffer and written to the Flash
device. First, the Write to Buffer Setup command is
issued along with the Block Address of the memory
device erase block to which the buffer content will
be written. At this point, the eXtended Status
Register (XSR) information (reference Table 7) is
loaded into the register and XSR.7 reverts to
reflecting
“buffer available” status. Whenever the
memory device is read immediately after receiving
a Write to Buffer command, the XSR content will be
presented by the memory. If XSR.7 = 0, the write
buffer is not available for writing. When XSR.7 =
“1,” the memory device will allow data to be written
to the write buffer. To determine when the write
buffer can be written, continue to monitor XSR.7
until XSR.7 = 1 by repeating the sequence of first
issuing the Write to Buffer Setup command along
with the appropriate Block Address, and then
reading the eXtended Status Register.
When the write buffer becomes available for writing,
a word count (N) is given to the memory device with
the Block Address of the memory device erase
block to which the buffer content will be written. On
the next write, a device start address is given along
with
the
write
buffer
programming performance and lower power, align
the start address at the beginning of a Write Buffer
boundary. Subsequent writes provide additional
device addresses and data. All subsequent
addresses must lie within the start address plus the
count.
data.
For
maximum
After the final buffer data is given, a Write Confirm
command is issued. This initiates the WSM (Write
State Machine) to begin copying the buffer data to
the flash memory. If a command other than Write
Confirm is written to the device, an “Invalid
Command/Sequence” error will be generated and
status register bits SR.5 and SR.4 will be set to a
“1.” For additional buffer writes, issue another Write
to Buffer Setup command and check XSR.7. The
write buffers can be loaded while the WSM is busy
as long as XSR.7 indicates that a buffer is
available.
If an error occurs while a device is writing data to
memory, the device will stop writing, and status
register bit SR.4 will be set to a “1” to indicate a
write operation failure. Any time a media failure
occurs during a write or an erase (for which SR.4 or
SR.5 is set, respectively), the device will not except
any more buffered write commands. Additionally, if
the user attempts to write past an erase block
boundary with a Write to Buffer command, the
device will abort the write. This will generate an
“Invalid Command/Sequence” error (“botch”) and
status register bits SR.5 and SR.4 will be set to a
“1.” To clear SR.4 and/or SR.5 issue a Clear Status
Register command.
Successful writing to an erase block requires that
the block’s associated Block Lock-Bit bit be reset. If
the Block Lock-Bit is set, the erase block is locked.
A Write to Buffer command which attempts to write
data to the locked block will fail and result in SR.1
and SR.4 being set to “1.”
5.2.2
CONFIGURATION COMMAND
The Configuration Command is not supported on
the 5 Volt Value Series 200 PC Card. The
Configuration Command serves to program the
configurable status output (STS output pin) of a
memory device. To satisfy the PCMCIA
PC Card
Specification
the STS output pin for all card
memory devices must be configured as a RY/BY#
pin to generate the card’s BUSY# output signal. At
card power-up the STS output for all devices
defaults to RY/BY# pin operation; thereafter, host
software
shall
not
issue
command.
the
Configuration
5.2.3
READ QUERY COMMAND
The SCS (Scaleable Command Set) Read Query
command causes the flash component to display
the Common Flash Interface (CFI) Query structure
or “database.” The Common Flash Interface
provides a standard means for a flash memory to
tell a host system about the memory's architecture,
algorithms
and
characteristics.
Common Flash Interface (CFI) and Command Sets
(order number 292204) for a full description of CFI.
See
AP-646
Writing the Read Query command to the memory
puts it in read query mode. While in read query
mode, the memory responds to read bus operations
with data from a ROM instead of data from the flash
array data. The data in the ROM describes the
memory component to which the Ready Query
command is addressed.
As the definition of CFI data presented by a card
memory device is quite extensive, the definition is
not repeated as part of the current document. Refer
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