參數(shù)資料
型號: IDTTSE2002B3CNRG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 25/30頁
文件大?。?/td> 423K
描述: IC TEMP SENS EEPROM DFN-8
標(biāo)準(zhǔn)包裝: 120
功能: 溫度監(jiān)控系統(tǒng)(傳感器)
傳感器類型: 內(nèi)部
感應(yīng)溫度: -20°C ~ 125°C
精確度: ±1°C(最小值)
拓?fù)洌?/td> ADC(三角積分型),控制邏輯,寄存器庫
輸出類型: 2 線串行,I²C?/SMBUS?
輸出警報:
輸出風(fēng)扇:
電源電壓: 3 V ~ 3.6 V
工作溫度: -20°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-VFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 8-VFQFPN(2x3)
包裝: 管件
25 of 30
May 12, 2010
 
IDT Confidential
HYST Bit Decode
Bit 8  SHDN-Shutdown. The thermal sensing device and A/D converters are disabled to save power, no events will be generated. When either of
the lock bits is set, this bit cannot be set until unlocked. However it can be cleared at any time. When in shutdown mode, the TSE2002B3C still
responds to commands normally, however bus timeout may or may not be supported in this mode.
'0' (default); The temperature monitor is active and converting
'1'; The temperature monitor is disabled and will not generate interrupts or update the temperature data.
Bit 7  TCRIT_LOCK; Locks the TCRIT Limit Register from being updated.
'0' (default; The TCRIT Limit Register can be updated normally.
'1'; The TCRIT Limit Register is locked and cannot be updated. Once this bit has been set, it cannot be cleared until an internal
power on reset.
Bit 6  EVENT_LOCK; Locks the High and Low Limit Registers from being updated.
'0' (default); The High and Low Limit Registers can be updated normally.
'1'; The High and Low Limit Registers are locked and cannot be updated. Once this bit has been set, it cannot be cleared until
an internal power on reset.
Bit 5  CLEAR; Clears the EVENT pin when it has been asserted. This bit is write only and will always read '0'.
'0'; does nothing
'1'; The EVENT
 pin is released and will not be asserted until a new interrupt condition occurs. This bit is ignored if the device
is operating in Comparator Mode. This bit is self clearing.
Bit 4  EVENT_STS; Indicates if the EVENT
 pin is asserted. This bit is read only.
0' (default); The EVENT pin is not asserted.
'1'; The EVENT
 pin is being asserted by the device.
Bit 3  EVENT_CTRL; Masks the EVENT
 pin from generating an interrupt. If either of the lock bits are set (bit 7 and bit 6), then this bit cannot be
altered.
'0' (default); The EVENT
 pin is disabled and will not generate interrupts.
'1'; The EVENT pin is enabled.
Bit 2  TCRIT_ONLY; Controls whether the EVENT
 pin will be asserted from a high / low out-of-limit condition. When the EVENT_LOCK bit is set,
this bit cannot be altered.
'0' (default); The EVENT
 pin will be asserted if the measured temperature is above the High Limit or below the Low Limit in
addition to if the temperature is above the TCRIT Limit.
'1'; The EVENT
 pin will only be asserted if the measured temperature is above the TCRIT Limit.
Bit 1  EVENT_POL; Controls the active state of the EVENT
 pin. The EVENT
 pin is driven to this state when it is asserted.
HYST[1:0]
Hysteresis
1
0
0
0
Disable hysteresis (default)
0
1
1.5癈
1
0
3癈
1
1
6癈
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