參數(shù)資料
型號： IDT82V3285EQG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 56/147頁
文件大?。?/td> 0K
描述： IC PLL WAN SE STRATUM 100TQFP
標(biāo)準(zhǔn)包裝： 1
類型： 時鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，PECL
輸出： CMOS，LVDS，PECL
電路數(shù)： 1
比率 - 輸入:輸出： 5:5
差分 - 輸入:輸出： 是/是
頻率 - 最大： 622.08MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
IDT82V3285
WAN PLL
Pin Description
16
December 9, 2008
ALE / SCLK
73
I
pull-down
CMOS
ALE: Address Latch Enable
In Multiplexed mode, the address on AD[7:0] pins is sampled into the device on the falling
edge of ALE.
SCLK: Shift Clock
In Serial mode, a shift clock is input on this pin.
Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated
on the active edge of SCLK. The active edge is determined by the CLKE.
In EPROM, Intel and Motorola modes, this pin should be connected to ground.
RDY
75
O
CMOS
RDY: Ready/Data Acknowledge
In Multiplexed and Intel modes, a high level on this pin indicates that a read/write cycle is
completed. A low level on this pin indicates that wait state must be inserted.
In Motorola mode, a low level on this pin indicates that valid information on the data bus is
ready for a read operation or acknowledges the acceptance of the written data during a write
operation.
In EPROM and Serial modes, this pin should be connected to ground.
JTAG (per IEEE 1149.1)
TRST
2
I
pull-down
CMOS
TRST: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port.
This pin should be connected to ground when JTAG is not used.
TMS
7
I
pull-up
CMOS
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK.
TCK
9
I
pull-down
CMOS
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely
retain their state.
TDI
23
I
pull-up
CMOS
TDI: JTAG Test Data Input
The test data is input on this pin. It is clocked into the device on the rising edge of TCK.
TDO
21
O
CMOS
TDO: JTAG Test Data Output
The test data is output on this pin. It is clocked out of the device on the falling edge of TCK.
TDO pin outputs a high impedance signal except during the process of data scanning.
This pin can indicate the interrupt of T0 selected input clock fail, as determined by the
LOS_FLAG_ON_TDO bit (b6, 0BH). Refer to Chapter 3.8.1 Input Clock Validity for details.
Power & Ground
VDDD1
VDDD2
VDDD3
VDDD4
VDDD5
VDDD6
VDDD7
12
16
13
50
61
85
86
Power
-
VDDDn: 3.3 V Digital Power Supply
VDDDn connections should be connected using the recommended decoupling scheme
shown in Figure 14.
Table 1: Pin Description (Continued)
Name
Pin No.
I/O
Type
Description 1
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT82V3285EQG8 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN SE STRATUM 100TQFP
IDT82V3288 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3288BC 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3288BCG 功能描述:IC PLL WAN 3E STRATUM 2 208CABGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDT82V3352 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SYNCHRONOUS ETHERNET WAN PLL
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