A 2 kHz, 4 kHz, N x 8 kHz
參數(shù)資料
型號: IDT82V3285EQG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 46/147頁
文件大?。?/td> 0K
描述: IC PLL WAN SE STRATUM 100TQFP
標準包裝: 1
類型: 時鐘/頻率發(fā)生器,多路復用器
PLL:
主要目的: 以太網,SONET/SDH,Stratum
輸入: CMOS,LVDS,PECL
輸出: CMOS,LVDS,PECL
電路數(shù): 1
比率 - 輸入:輸出: 5:5
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP 裸露焊盤
供應商設備封裝: 100-TQFP-EP(14x14)
包裝: 托盤
IDT82V3285
WAN PLL
Pin Description
14
December 9, 2008
IN5
54
I
pull-down
CMOS
IN5: Input Clock 5
A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
In Slave operation, the frequency of the T0 selected input clock IN5 is recommended to be
6.48 MHz.
Output Frame Synchronization Signal
FRSYNC_8K
30
O
CMOS
FRSYNC_8K: 8 kHz Frame Sync Output
An 8 kHz signal is output on this pin.
MFRSYNC_2K
31
O
CMOS
MFRSYNC_2K: 2 kHz Multiframe Sync Output
A 2 kHz signal is output on this pin.
Output Clock
OUT1
90
O
CMOS
OUT1: Output Clock 1
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz or 155.52 MHz clock is output on this pin.
OUT2
93
O
CMOS
OUT2: Output Clock 2
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz or 155.52 MHz clock is output on this pin.
OUT3
94
O
CMOS
OUT3: Output Clock 3
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz or 155.52 MHz clock is output on this pin.
OUT4_POS
OUT4_NEG
34
35
O
PECL/LVDS
OUT4_POS / OUT4_NEG: Positive / Negative Output Clock 4
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz clock is differentially output on this pair
of pins.
OUT5_POS
OUT5_NEG
36
37
O
PECL/LVDS
OUT5_POS / OUT5_NEG: Positive / Negative Output Clock 5
A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7,
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz clock is differentially output on this pair
of pins.
Microprocessor Interface
CS
70
I
pull-up
CMOS
CS: Chip Selection
A transition from high to low must occur on this pin for each read or write operation and this
pin should remain low until the operation is over.
INT_REQ
8
O
CMOS
INT_REQ: Interrupt Request
This pin is used as an interrupt request. The output characteristics are determined by the
HZ_EN bit (b1, 0CH) and the INT_POL bit (b0, 0CH).
Table 1: Pin Description (Continued)
Name
Pin No.
I/O
Type
Description 1
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IDT82V3285EQG8 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN SE STRATUM 100TQFP
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