參數(shù)資料
型號: IDT82V3285EQG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 143/147頁
文件大?。?/td> 0K
描述: IC PLL WAN SE STRATUM 100TQFP
標準包裝: 1
類型: 時鐘/頻率發(fā)生器,多路復用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,PECL
輸出: CMOS,LVDS,PECL
電路數(shù): 1
比率 - 輸入:輸出: 5:5
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP 裸露焊盤
供應商設備封裝: 100-TQFP-EP(14x14)
包裝: 托盤
IDT82V3285
WAN PLL
Programming Information
95
December 9, 2008
IN5_STS - Input Clock 5 Status
Address: 48H
Type: Read
Default Value: X110X110
Bit
Name
Description
7 - 3
-
Reserved.
2
IN5_FREQ_HARD_ALARM
This bit indicates whether IN5 is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
1
IN5_NO_ACTIVITY_ALARM
This bit indicates whether IN5 is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
0
IN5_PH_LOCK_ALARM
This bit indicates whether IN5 is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H)
X MULTI_FACTOR[1:0] (b7~6, 08H) in seconds) which starts from when the alarm is raised.
7
6543
210
----
-
IN5_FREQ_HA
RD_ALARM
IN5_NO_ACTIV
ITY_ALARM
IN5_PH_LOCK
_ALARM
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相關代理商/技術參數(shù)
參數(shù)描述
IDT82V3285EQG8 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN SE STRATUM 100TQFP
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