參數(shù)資料
型號： IDT82V3285EQG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 112/147頁
文件大小： 0K
描述： IC PLL WAN SE STRATUM 100TQFP
標準包裝： 1
類型： 時鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，PECL
輸出： CMOS，LVDS，PECL
電路數(shù)： 1
比率 - 輸入:輸出： 5:5
差分 - 輸入:輸出： 是/是
頻率 - 最大： 622.08MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
IDT82V3285
WAN PLL
Programming Information
67
December 9, 2008
MON_SW_PBO_CNFG - Frequency Monitor, Input Clock Selection & PBO Control
Address: 0BH
Type: Read / Write
Default Value: 100X01X1
Bit
Name
Description
7
FREQ_MON_CLK
The bit selects a reference clock for input clock frequency monitoring.
0: The output of T0 DPLL.
1: The master clock. (default)
6
LOS_FLAG_TO_TDO
The bit determines whether the interrupt of T0 selected input clock fail - is reported by the TDO pin.
0: Not reported. TDO pin is used as JTAG test data output which complies with IEEE 1149.1. (default)
1: Reported. TDO pin mimics the state of the T0_MAIN_REF_FAILED bit (b6, 0EH) and does not strictly comply with IEEE
1149.1.
5
ULTR_FAST_SW
This bit determines whether the T0 selected input clock is valid when missing 2 consecutive clock cycles or more.
0: Valid. (default)
1: Invalid.
4EXT_SW
This bit determines the T0 input clock selection.
0: Forced selection or Automatic selection, as controlled by the T0_INPUT_SEL[3:0] bits (b3~0, 50H).
1: External Fast selection.
The default value of this bit is determined by the FF_SRCSW pin during reset.
3
PBO_FREZ
This bit is valid only when the PBO is enabled by the PBO_EN bit (b2, 0BH). It determines whether PBO is frozen at the cur-
rent phase offset when a PBO event is triggered.
0: Not frozen. (default)
1: Frozen. Further PBO events are ignored and the current phase offset is maintained.
2
PBO_EN
This bit determines whether PBO is enabled when the T0 selected input clock switch or the T0 DPLL exiting from Holdover
mode or Free-Run mode occurs.
0: Disabled.
1: Enabled. (default)
1-
Reserved.
0
FREQ_MON_HARD_EN
This bit determines whether the frequency hard alarm is enabled when the frequency of the input clock with respect to the
reference clock is above the frequency hard alarm threshold. The reference clock can be the output of T0 DPLL or the mas-
ter clock, as determined by the FREQ_MON_CLK bit (b7, 0BH).
0: Disabled.
1: Enabled. (default)
76
5
4321
0
FREQ_MON_C
LK
LOS_FLAG_TO
_TDO
ULTR_FAST_SW
EXT_SW
PBO_FREZ
PBO_EN
-
FREQ_MON_H
ARD_EN
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT82V3285EQG8 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN SE STRATUM 100TQFP
IDT82V3288 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3288BC 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3288BCG 功能描述:IC PLL WAN 3E STRATUM 2 208CABGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDT82V3352 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SYNCHRONOUS ETHERNET WAN PLL
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