參數(shù)資料
型號: IDT82V3285EQG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 145/147頁
文件大小: 0K
描述: IC PLL WAN SE STRATUM 100TQFP
標準包裝: 1
類型: 時鐘/頻率發(fā)生器,多路復用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,PECL
輸出: CMOS,LVDS,PECL
電路數(shù): 1
比率 - 輸入:輸出: 5:5
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 托盤
IDT82V3285
WAN PLL
Programming Information
97
December 9, 2008
REMOTE_INPUT_VALID2_CNFG - Input Clocks Validity Configuration 2
PRIORITY_TABLE1_STS - Priority Status 1 *
Address: 4DH
Type: Read / Write
Default Value: XX111111
Bit
Name
Description
7 - 3
-
Reserved.
2IN5_VALID
This bit controls whether IN5 is allowed to be locked for automatic selection.
0: Enabled.
1: Disabled. (default)
1 - 0
-
Reserved.
Address: 4EH
Type: Read
Default Value: 00000000
Bit
Name
Description
7 - 4
HIGHEST_PRIORITY_VALIDATED[3:0]
These bits indicate a qualified input clock with the highest priority.
0000: No input clock is qualified. (default)
0001, 0010: Reserved.
0011: IN1.
0100: IN2.
0101: IN3.
0110: IN4.
0111, 1000, 1001, 1010: Reserved.
1011: IN5.
1100, 1101, 1110, 1111: Reserved.
Note that the input clock is indicated by these bits only when the corresponding INn (b5-2, 4CH) or INn
(b2, 4DH) bit is ‘0’.
3 - 0
CURRENTLY_SELECTED_INPUT[3:0]
These bits indicate the T0/T4 selected input clock.
0000: No input clock is selected; or the T4 selected input clock is the T0 DPLL output. (default)
0001, 0010: Reserved.
0011: IN1 is selected.
0100: IN2 is selected.
0101: IN3 is selected.
0110: IN4 is selected.
0111, 1000, 1001, 1010: Reserved.
1011: IN5 is selected.
1100, 1101, 1110, 1111: Reserved.
Note that the input clock is indicated by these bits only when the corresponding INn (b5-2, 4CH) or INn
(b2, 4DH) bit is ‘0’.
7
6543
210
----
-
IN5_VALID
--
7
6543
210
HIGHEST_PRI
ORITY_VALIDA
TED3
HIGHEST_PRI
ORITY_VALIDA
TED2
HIGHEST_PRI
ORITY_VALIDA
TED1
HIGHEST_PRI
ORITY_VALIDA
TED0
CURRENTLY_S
ELECTED_INP
UT3
CURRENTLY_S
ELECTED_INP
UT2
CURRENTLY_S
ELECTED_INP
UT1
CURRENTLY_S
ELECTED_INP
UT0
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