參數(shù)資料
型號(hào)： IDT82V2051EPP
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 7/61頁(yè)
文件大小： 0K
描述： IC LIU E1 SGL SHORT HAUL 44-TQFP
標(biāo)準(zhǔn)包裝： 80
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 44-LQFP
供應(yīng)商設(shè)備封裝： 44-TQFP（10x10）
包裝： 托盤
其它名稱： 82V2051EPP
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Functional Description
15
December 9, 2005
3
FUNCTIONAL DESCRIPTION
3.1
CONTROL MODE SELECTION
The IDT82V2051E can be configured by software or by hardware. The
software control mode supports Serial Control Interface, Motorola Multi-
plexed Control Interface and Intel Multiplexed Control Interface. The Con-
trol mode is selected by MODE1 and MODE0 pins as follows:
The serial microcontroller Interface consists of CS, SCLK, SCLKE,
SDI, SDO and INT pins. SCLKE is used for the selection of active
edge of SCLK.
The parallel Multiplexed microcontroller Interface consists of CS,
AD[7:0], DS/RD, R/W/WR, ALE/AS, ACK/RDY and INT pins.
Hardware interface consists of PULS, THZ, RCLKE, LP[1:0],
PATT[1:0], JA[1:0], MONT, TERM, RPD, MODE[1:0] and
RXTXM[1:0]. Refer to 5 Hardware Control Pin Summary for details
about hardware control.
3.2
TRANSMIT PATH
The transmit path of IDT82V2051E consists of an Encoder, an optional
Jitter Attenuator, a Waveform Shaper, a Line Driver and a Programmable
Transmit Termination.
3.2.1
TRANSMIT PATH SYSTEM INTERFACE
The transmit path system interface consists of TCLK pin, TD/TDP pin
and TDN pin. TCLK is a 2.048 MHz clock. If TCLK is missing for more than
70 MCLK cycles, an interrupt will be generated if it is not masked.
Transmit data is sampled on the TD/TDP and TDN pins by the active
edge of TCLK. The active edge of TCLK can be selected by the TCLK_SEL
bit (TCF0, 05H). And the active level of the data on TD/TDP and TDN can
be selected by the TD_INV bit (TCF0, 05H). In hardware control mode, the
falling edge of TCLK and the active high of transmit data are always used.
The transmit data from the system side can be provided in two different
ways: Single Rail and Dual Rail. In Single Rail mode, only TD pin is used
for transmitting data and the T_MD[1] bit (TCF0, 05H) should be set to ‘0’.
In Dual Rail Mode, both TDP pin and TDN pin are used for transmitting data,
the T_MD[1] bit (TCF0, 05H) should be set to ‘1’.
3.2.2
ENCODER
In Single Rail mode, the Encoder can be configured to be a HDB3
encoder or an AMI encoder by setting T_MD[0] bit (TCF0, 05H).
In Dual Rail mode, the Encoder is by-passed. In Dual Rail mode, a logic
‘1’ on the TDP pin and a logic ‘0’ on the TDN pin results in a negative pulse
on the TTIP/TRING; a logic ‘0’ on TDP pin and a logic ‘1’ on TDN pin results
in a positive pulse on the TTIP/TRING. If both TDP and TDN are high or low,
the TTIP/TRING outputs a space (Refer to TD/TDP, TDN Pin Description).
In hardware control mode, the operation mode of receive and transmit
path can be selected by setting RXTXM1 and RXTXM0 pins. Refer to 5
3.2.3
PULSE SHAPER
The IDT82V2051E provides two ways of manipulating the pulse shape
before sending it. One is to use preset pulse templates, the other is to use
user-programmable arbitrary waveform template.
In software control mode, the pulse shape can be selected by setting
the related registers.
In hardware control mode, the pulse shape can be selected by setting
PULS pin. Refer to 5 Hardware Control Pin Summary for details.
3.2.3.1 PRESET PULSE TEMPLATES
The pulse shape is shown in Figure-3 according to the G.703 and the
measuring diagram is shown in Figure-4. In internal impedance matching
mode, if the cable impedance is 75
, the PULS[3:0] bits (TCF1, 06H)
should be set to ‘0000’; if the cable impedance is 120
, the PULS[3:0] bits
(TCF1,06H)shouldbesetto‘0001’.Inexternalimpedancematchingmode,
for both E1/75
and E1/120 cable impedance, PULS[3:0] should be set
to ‘0001’.
Figure-3 E1 Waveform Template Diagram
Figure-4 E1 Pulse Template Test Circuit
Control Interface mode
00
Hardware interface
01
Serial Microcontroller Interface.
10
Parallel –Multiplexed -Motorola Interface
11
Parallel –Multiplexed -Intel Interface
-0 .6
-0 .4
-0 .2
0
0 .2
0 .4
0.6
-0 .2 0
0.00
0.20
0.40
0.60
0.8 0
1.0 0
1.20
T im e in U n it In te rva ls
N
or
m
alized
Am
plit
ude
IDT82V2051E
VOUT
RLOAD
TTIP
TRING
Note: 1. For RLOAD = 75
(nom), Vout (Peak) = 2.37 V (nom)
2. For RLOAD = 120
(nom), Vout (Peak) = 3.00 V (nom)
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