參數(shù)資料
型號(hào)： IDT82V2051EPP
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 33/61頁(yè)
文件大?。?/td> 0K
描述： IC LIU E1 SGL SHORT HAUL 44-TQFP
標(biāo)準(zhǔn)包裝： 80
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 44-LQFP
供應(yīng)商設(shè)備封裝： 44-TQFP（10x10）
包裝： 托盤
其它名稱： 82V2051EPP
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Programming Information
39
December 9, 2005
4.3.4
NETWORK DIAGNOSTICS CONTROL REGISTERS
Table-27 MAINT0: Maintenance Function Control Register 0
(R/W, Address = 0DH)
Symbol
Bit
Default
Description
-
7
00
Reserved.
PATT[1:0]
6-5
00
These bits select the internal pattern and insert it into transmit data stream.
= 00: Normal operation (PATT_CLK = 0) / insert all zeros (PATT_CLK = 1)
= 01: Insert All Ones
= 10: Insert PRBS (E1: 215-1)
= 11: Reserved
PATT_CLK
4
0
Selects reference clock for transmitting internal pattern
= 0: Uses TCLK as the reference clock
= 1: Uses MCLK as the reference clock
PRBS_INV
3
0
Inverts PRBS
= 0: The PRBS data is not inverted
= 1: The PRBS data is inverted before transmission and detection
LAC
2
0
LOS/AIS criterion is selected as below:
= 0: G.775
= 1: ETSI 300233& I.431
AISE
1
0
AIS enable during LOS
= 0: AIS insertion on RDP/RDN/RCLK is disabled during LOS
= 1: AIS insertion on RDP/RDN/RCLK is enabled during LOS
ATAO
0
Automatically Transmit All Ones (enabled only when PATT[1:0] = 00)
= 0: Disabled
= 1: Automatically Transmit All Ones pattern at TTIP/TRING during LOS
Table-28 MAINT1: Maintenance Function Control Register 1
(R/W, Address= 0EH)
Symbol
Bit
Default
Description
-
7-3
00000
Reserved
RLP
2
0
Remote loopback enable
= 0: Disables remote loopback (normal transmit and receive operation)
= 1: Enables remote loopback
ALP
1
0
Analog loopback enable
= 0: Disables analog loopback (normal transmit and receive operation)
= 1: Enables analog loopback
DLP
0
Digital loopback enable
= 0: Disables digital loopback (normal transmit and receive operation)
= 1: Enables digital loopback
Table-29 MAINT6: Maintenance Function Control Register 6
(R/W, Address = 13H)
Symbol
Bit
Default
Description
-
7
0
Reserved.
BPV_INS
6
0
BPV error insertion
A ‘0’ to ‘1’ transition on this bit will cause a single bipolar violation error to be inserted into the transmit data stream.
This bit must be cleared and set again for a subsequent error to be inserted.
ERR_INS
5
0
PRBS logic error insertion
A ‘0’ to ‘1’ transition on this bit will cause a single PRBS logic error to be inserted into the transmit PRBS data stream.
This bit must be cleared and set again for a subsequent error to be inserted.
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