參數(shù)資料
型號(hào)： IDT82V2051EPP
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 14/61頁
文件大?。?/td> 0K
描述： IC LIU E1 SGL SHORT HAUL 44-TQFP
標(biāo)準(zhǔn)包裝： 80
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 44-LQFP
供應(yīng)商設(shè)備封裝： 44-TQFP（10x10）
包裝： 托盤
其它名稱： 82V2051EPP
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Functional Description
21
December 9, 2005
3.3.8
RECEIVE PATH SYSTEM INTERFACE
The receive path system interface consists of RCLK pin, RD/RDP pin
and RDN pin. The RCLK outputs a recovered 2.048 MHz clock. The
received data is updated on the RD/RDP and RDN pins on the active edge
of RCLK. The active edge of RCLK can be selected by the RCLK_SEL bit
(RCF0, 0AH). And the active level of the data on RD/RDP and RDN can be
selected by the RD_INV bit (RCF0, 0AH).
In hardware control mode, only the active edge of RCLK can be
selected.IfRCLKEissettohigh,thefallingedgewillbechosenastheactive
edge of RCLK. If RCLKE is set to low, the rising edge will be chosen as the
active edge of RCLK. The active level of the data on RD/RDP and RDN is
the same as that in software control mode.
Thereceiveddatacanbeoutputtothesystemsideintwodifferentways:
Single Rail or Dual Rail, as selected by R_MD bit [1] (RCF0, 0AH). In Single
Rail mode, only RD pin is used to output data and the RDN/CV pin is used
to report the received errors. In Dual Rail Mode, both RDP pin and RDN pin
are used for outputting data.
In the receive Dual Rail mode, the CDR unit can be by-passed by setting
R_MD[1:0] to ‘11’ (binary). In this situation, the output data from the Data
Slicer will be output to the RDP/RDN pins directly, and the RCLK outputs
the exclusive OR (XOR) of the RDP and RDN. This is called receiver slicer
mode. In this case, the transmit path is still operating in Dual Rail mode.
3.3.9
RECEIVE PATH POWER DOWN
The receive path can be powered down by setting R_OFF bit (RCF0,
0AH) to‘1’.Inthiscase, the RCLK,RD/RDP,RDNandLOSwillbelogiclow.
In hardware control mode, receiverpower down can be selected by pull-
ing RPD pin to high. Refer to 5 Hardware Control Pin Summary for more
details.
3.4
JITTER ATTENUATOR
There is one JitterAttenuator in the IDT82V2051E.TheJitter Attenuator
can be deployed in the transmit path or the receive path, and can also be
disabled. This is selected by the JACF[1:0] bits (JACF, 04H).
In hardware control mode, Jitter Attenuator position, bandwidth and the
depth of FIFO can be selected by JA[1:0] pins. Refer to 5 Hardware Control
Pin Summary for details.
3.4.1
JITTER ATTENUATION FUNCTION DESCRIPTON
The Jitter Attenuator is composed of a FIFO and a DPLL, as shown in
Figure-9. The FIFO is used as a pool to buffer the jittered input data, then
the data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the JADP[1:0] bits
(JACF, 04H). In hardware control mode, the depth of FIFO can be selected
by JA[1:0] pins. Refer to 5 Hardware Control Pin Summary for details. Con-
sequently, the constant delay of the Jitter Attenuator will be 16 bits, 32 bits
or 64 bits. Deeper FIFO can tolerate larger jitter, butat the cost of increasing
data latency time.
Figure-9 Jitter Attenuator
The Corner Frequency of the DPLL can be 0.9 Hz or 6.8 Hz, as selected
bytheJABWbit(JACF,04H).ThelowertheCornerFrequencyis,thelonger
time is needed to achieve synchronization.
When the incoming data moves faster than the outgoing data, the FIFO
will overflow. This overflow is captured by the JAOV_IS bit (INTS1, 1AH).
If the incoming data moves slower than the outgoing data, the FIFO will
underflow. This underflow is captured by the JAUD_IS bit (INTS1, 1AH). For
some applications that are sensitive to data corruption, the JA limit mode
can be enabled by setting JA_LIMIT bit (JACF, 04H) to ‘1’. In the JA limit
mode, the speed of the outgoing data will be adjusted automatically when
theFIFOisclosetoitsfulloremptiness.Thecriteriaofstartingspeedadjust-
ment are shown in Table-6. The JA limit mode can reduce the possibility of
FIFO overflow and underflow, but the quality of jitter attenuation is deteri-
orated.
FIFO
32/64/128
DPLL
Jittered Data
De-jittered Data
Jittered Clock
De-jittered Clock
MCLK
W
R
RCLK
RD/RDP
RDN
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