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參數(shù)資料
| 型號(hào)： | IDT82V2051EPP |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 17/61頁 |
| 文件大小： | 0K |
| 描述： | IC LIU E1 SGL SHORT HAUL 44-TQFP |
| 標(biāo)準(zhǔn)包裝： | 80 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應(yīng)商設(shè)備封裝： | 44-TQFP（10x10） |
| 包裝： | 托盤 |
| 其它名稱： | 82V2051EPP |
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IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Functional Description
24
December 9, 2005
3.6
TRANSMIT AND DETECT INTERNAL PATTERNS
Theinternal patterns(AllOnes,All Zeros andPRBS pattern) will be gen-
erated anddetected by IDT82V2051E.TCLK isused as thereference clock
by default. MCLK can also be used as the reference clock by setting the
PATT_CLK bit (MAINT0, 0DH) to ‘1’.
If the PATT_CLK bit (MAINT0, 0DH) is set to ‘0’ and the PATT[1:0] bits
(MAINT0,0DH)aresetto‘00’,thetransmitpathwilloperateinnormalmode.
When the chip is configured by hardware, the transmit path will operate
in normal mode by setting PATT[1:0] pins to ‘00’. Refer to 5 Hardware Con-
trol Pin Summary for details.
3.6.1
TRANSMIT ALL ONES
In transmit direction, the All Ones data can be inserted into the data
streamwhenthePATT[1:0]bits(MAINT0,0DH)aresetto‘01’.Thetransmit
data stream is output from TTIP/TRING. In this case, either TCLK or MCLK
can be used as the transmit clock, as selected by the PATT_CLK bit
(MAINT0, 0DH).
Inhardwarecontrolmode,theAllOnesdatacanbeinsertedintothedata
stream in transmit direction by setting PATT[1:0] pins to ‘01’. Refer to 5
Hardware Control Pin Summary for details.
3.6.2
TRANSMIT ALL ZEROS
If the PATT_CLK bit (MAINT0, 0DH) is set to ‘1’, the All Zeros will be
inserted into the transmit data stream when the PATT[1:0] bits (MAINT0,
0DH) are set to ‘00’.
3.6.3
PRBS GENERATION AND DETECTION
A PRBS will be generated in the transmit direction and detected in the
receive direction by IDT82V2051E. The PRBS is 215-1, with maximum zero
restrictions according to ITU-T O.151.
When the PATT[1:0] bits (MAINT0, 0DH) are set to ‘10’, the PRBS pat-
tern will be inserted into the transmit data stream with the MSB first. The
PRBS pattern will be transmitted directly or invertedly.
In hardware control mode, the PRBS data will be generated in the trans-
mitdirectionandinsertedintothetransmitdatastreambysettingPATT[1:0]
pins to ‘10’. Refer to 5 Hardware Control Pin Summary for details.
The PRBS in the received data stream will be monitored. If the PRBS
has reached synchronization status, the PRBS_S bit (STAT0, 17H) will be
set to ‘1’, even in the presence of a logic error rate less than or equal to 10-
1. The criteria for setting/clearing the PRBS_S bit are shown in Table-10.
PRBS data canbe inverted throughsetting the PRBS_INVbit(MAINT0,
0DH).
Any change of PRBS_S bit will be captured by PRBS_IS bit (INTS0,
19H). The PRBS_IES bit (INTES, 16H) can be used to determine whether
the ‘0’ to ‘1’ change of PRBS_S bit will be captured by the PRBS_IS bit or
any changes of PRBS_S bit will be captured by the PRBS_IS bit. When the
PRBS_IS bit is ‘1’, an interruptwill be generated if the PRBS_IM bit (INTM0,
14H) is set to ‘1’.
The received PRBS logic errors can be counted in a 16-bit counter if the
ERR_SEL [1:0] bits (MAINT6, 13H) are set to ‘00’. Refer to 3.8 Error Detec-
tion/Counting And Insertion for the operation of the error counter.
3.7
LOOPBACK
To facilitate testing and diagnosis, the IDT82V2051E provides three dif-
ferent loopback configurations: Analog Loopback, Digital Loopback and
Remote Loopback.
3.7.1
ANALOG LOOPBACK
When the ALP bit (MAINT1, 0EH) is set to ‘1’, the chip is configured in
Analog Loopback mode. In this mode, the transmit signals are looped back
to the Receiver Internal Termination in the receive path then output from
RCLK, RD, RDP/RDN. At the same time, the transmit signals are still output
to TTIP/TRING in transmit direction. The all-ones pattern can be generated
during analog loopback. Figure-11 shows the process.
3.7.2
DIGITAL LOOPBACK
When the DLP bit (MAINT1, 0EH) is set to ‘1’, the chip is configured in
Digital Loopback mode. In this mode, the transmit signals are looped back
to the jitter attenuator (if enabled) and decoder in receive path, then output
from RCLK, RD, RDP/RDN. At the same time, the transmit signals are still
output to TTIP/TRING in transmit direction. Figure-12 shows the process.
Both Analog Loopback mode and Digital Loopback mode allow the
sending of the internal patterns (All Ones, All Zeros, PRBS, etc.) which will
overwrite the transmit signals. In this case, either TCLK or MCLK can be
used as the reference clock for internal patterns transmission.
In hardware control mode, Digital Loopback can be selected by setting
LP[1:0] pins to ‘10’.
3.7.3
REMOTE LOOPBACK
When the RLP bit (MAINT1, 0EH) is set to ‘1’, the chip is configured in
Remote Loopback mode. In this mode, the recovered clock and data output
from Clock and Data Recovery on the receive path is looped back to the
jitter attenuator (if enabled) and Waveform Shaper in transmit path. Figure-
13 shows the process.
Inhardwarecontrolmode,RemoteLoopbackcanbeselectedbysetting
LP[1:0] pins to ‘11’.
Table-10 Criteria for Setting/Clearing the PRBS_S Bit
PRBS Detection 6 or less than 6 bit errors detected in a 64 bits hopping win-
dow.
PRBS Missing
More than 6 bit errors detected in a 64 bits hopping window.
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