參數(shù)資料
型號： IDT82V2051EPP
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 22/61頁
文件大?。?/td> 0K
描述： IC LIU E1 SGL SHORT HAUL 44-TQFP
標準包裝： 80
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 44-LQFP
供應商設備封裝： 44-TQFP（10x10）
包裝： 托盤
其它名稱： 82V2051EPP
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Functional Description
29
December 9, 2005
3.10 MCLK AND TCLK
3.10.1 MASTER CLOCK (MCLK)
MCLK is an independent, free-running reference clock. MCLK is 2.048
MHz. This reference clock is used to generate several internal reference
signals:
Timing reference for the integrated clock recovery unit.
Timing reference for the integrated digital jitter attenuator.
Timing reference for microcontroller interface.
Generation of RCLK signal during a loss of signal condition if AIS is
enabled.
Reference clock during Transmit All Ones, All Zeros and PRBS pat-
tern if it is selected as the reference clock. For ATAO and AIS,
MCLK is always used as the reference clock.
Reference clock during Transmit All Ones (TAO) condition or send-
ing PRBS in hardware control mode.
Figure-16 shows the chip operation status in different conditions of
MCLK and TCLK. The missing of MCLK will set the TTIP/TRING to high
impedance state.
3.10.2 TRANSMIT CLOCK (TCLK)
TCLK is used to sample the transmit data on TD/TDP and TDN. The
active edge of TCLK can be selected by the TCLK_SEL bit (TCF0, 05H).
During Transmit All Ones or PRBS patterns, either TCLK or MCLK can be
used as the reference clock. This is selected by the PATT_CLK bit
(MAINT0, 0DH).
But for Automatic Transmit All Ones and AIS, only MCLK is used as the
reference clock and the PATT_CLK bit is ignored. In Automatic Transmit
All Ones condition, the ATAO bit (MAINT0, 0DH) is set to ‘1’. In AIS condi-
tion, the AISE bit (MAINT0, 0DH) is set to ‘1’.
If TCLK has been missing for more than 70 MCLK cycles, TCLK_LOS
bit (STAT0, 17H) will be set, and the TTIP/TRING will become high imped-
anceifthechipisnotusedforremoteloopbackorisnotusingMCLKtotrans-
mit internal patterns (TAOS, All Zeros and PRBS). When TCLK is detected
again, TCLK_LOS bit (STAT0, 17H) will be cleared. The reference fre-
quency to detect a TCLK loss is derived from MCLK.
Figure-16 TCLK Operation Flowchart
transmitter high impedance
yes
MCLK=H/L?
normal operation
Clocked
TCLK status?
L/H
clocked
generate transmit clock loss
interrupt if not masked in
software control mode;
transmitter high impedance
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相關代理商/技術參數(shù)
參數(shù)描述
IDT82V2051EPP8 功能描述:IC LIU E1 SGL SHORT HAUL 44-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR)
IDT82V2051EPPG 功能描述:IC LIU E1 SGL SHORT HAUL 44-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR)
IDT82V2051EPPG8 功能描述:IC LIU E1 SGL SHORT HAUL 44-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR)
IDT82V2052E 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
IDT82V2052EPF 功能描述:IC LIU E1 2CH SHORT HAUL 80-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR)
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