T
參數(shù)資料
型號(hào)： IDT82P2828BHG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 84/154頁
文件大?。?/td> 0K
描述： IC LIU T1/J1/E1 28+1CH 640-PBGA
標(biāo)準(zhǔn)包裝： 5
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 640-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 640-PBGA-EP（31x31）
包裝： 托盤
其它名稱： 82P2828BHG
IDT82P2828
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Functional Description
35
February 6, 2009
3.3.2
TX CLOCK RECOVERY
The Tx Clock Recovery is used only when the transmit system inter-
face is in Dual Rail RZ Format mode. When the transmit system inter-
face is in other modes, the Tx Clock Recovery is bypassed
automatically.
The Tx Clock Recovery is used to recover the clock signal from the
data input on TDPn and TDNn.
3.3.3
ENCODER
The Encoder is used only when the transmit system interface is in
Single Rail NRZ Format mode. When the transmit system interface is in
other modes, the Encoder is bypassed automatically.
In T1/J1 mode, the data to be transmitted is encoded by AMI or
B8ZS line code rule. In E1 mode, the data to be transmitted is encoded
by AMI or HDB3 line code rule. The line code rule is selected by the
T_CODE bit (b2, TCF1,...).
3.3.4
WAVEFORM SHAPER
The IDT82P2828 provides two ways to manipulate the pulse shape
before data is transmitted:
Preset Waveform Template;
User-Programmable Arbitrary Waveform.
3.3.4.1 Preset Waveform Template
In T1/J1 applications, the waveform template meets T1.102. The T1
template is shown in Figure-15. It is measured in the far end, as shown
in Figure-16. The J1 template is measured in the near end line side.
In T1 applications, to meet the template, five preset waveform
templates are provided according to five grades of cable length. The
selection is made by the PULS[3:0] bits (b3~0, PULS,...). In J1 applica-
tions, the PULS[3:0] bits (b3~0, PULS,...) should be set to ‘0111’. Refer
to Table-5 for details.
Figure-15 DSX-1 Waveform Template
Figure-16 T1 Waveform Template Measurement Circuit
Table-4 Multiplex Pin Used in Transmit System Interface
Transmit System
Interface
Multiplex Pin Used On Transmit System
Interface
TDn / TDPn
TDNn / TMFn
TCLKn / TDNn
Single Rail NRZ Format
TDn 1
TMFn 2
TCLKn 3
Dual Rail NRZ Format
TDPn 1
TDNn 1
TCLKn 3
Dual Rail RZ Format
TDPn 1
TMFn 2
TDNn 1
Note:
1. The active level on TDn, TDPn and TDNn is selected by the TD_INV bit (b3,
2. TMFn is always active high.
3. The active edge of TCLKn is selected by the TCK_ES bit (b4, TCF1,...). If TCLKn is
missing, i.e., no transition for more than 64 T1/E1 clock cycles, the TCKLOS_S bit (b3,
STAT0,...) will be set. A transition from ‘0’ to ‘1’ on the TCKLOS_S bit (b3, STAT0,...) or
any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the TCKLOS_S bit (b3, STAT0,...) will
set the TCKLOS_IS bit (b3, INTS0,...) to ‘1’, as selected by the TCKLOS_IES bit (b3,
INTES,...). When the TCKLOS_IS bit (b3, INTS0,...) is ‘1’, an interrupt will be reported
by INT if not masked by the TCKLOS_IM bit (b3, INTM0,...).
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
0
250
500
750
1000
1250
Time (ns)
Nor
m
al
iz
ed
Ampl
itude
IDT82P2828
TTIPn
TRINGn
Cable
RLOAD VOUT
Note: RLOAD = 100
+ 5%
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