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參數(shù)資料
| 型號： | IDT82P2828BHG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 82/154頁 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/J1/E1 28+1CH 640-PBGA |
| 標(biāo)準(zhǔn)包裝： | 5 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 640-BGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 640-PBGA-EP（31x31） |
| 包裝： | 托盤 |
| 其它名稱： | 82P2828BHG |
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IDT82P2828
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Functional Description
33
February 6, 2009
3.2.3
SLICER
The Slicer is used to generate a standard amplitude mark or a space
according to the amplitude of the input signals. The input signal is sliced
at 50% of the peak value.
3.2.4
RX CLOCK & DATA RECOVERY
The Rx Clock & Data Recovery is used to recover the clock signal
from the received data. It is accomplished by an integrated Digital Phase
Locked Loop (DPLL). The recovered clock tracks the jitter in the data
output from the Slicer and keeps the phase relationship between data
and clock during the absence of the incoming pulse.
Note that the IDT82P2828 also provides programmable REFA and
REFB pins to output any of the 29 recovered line clocks. Refer to
Section 3.6 Clock Inputs and Outputs for details.
3.2.5
DECODER
The Decoder is used only when the receive system interface is in
Single Rail NRZ Format mode. When the receive system interface is in
other modes, the Decoder is bypassed automatically. (Refer to
Section 3.2.6 Receive System Interface for the description of the receive
system interface).
In T1/J1 mode, the received signal is decoded by AMI or B8ZS line
code rule. In E1 mode, the received signal is decoded by AMI or HDB3
line code rule. The line code rule is selected by the R_CODE bit (b2,
3.2.6
RECEIVE SYSTEM INTERFACE
The received data can be output to the system side in four modes:
Single Rail NRZ Format mode, Dual Rail NRZ Format mode, Dual Rail
RZ Format mode and Dual Rail Sliced mode, as selected by the
R_MD[1:0] bits (b1~0, RCF1).
If data is output on RDn in NRZ format and the recovered clock is
output on RCLKn, the receive system interface is in Single Rail NRZ
Format mode. In this mode, the data is decoded and updated on the
active edge of RCLKn. RCLKn outputs a 1.544 MHz (in T1/J1 mode) or
2.048 MHz (in E1 mode) clock. The Receive Multiplex Function (RMFn)
signal is updated on the active edge of RCLKn and can be selected to
indicate PRBS/ARB, LAIS, LEXZ, LBPV, LEXZ + LBPV, LLOS, output
recovered clock (RCLK) or XOR output of positive and negative sliced
data. Refer to Section 3.5.7.1 RMFn Indication for the description of
RMFn.
If data is output on RDPn and RDNn in NRZ format and the recov-
ered clock is output on RCLKn, the receive system interface is in Dual
Rail NRZ Format mode. In this mode, the data is un-decoded and
updated on the active edge of RCLKn. RCLKn outputs a 1.544 MHz (in
T1/J1 mode) or 2.048 MHz (in E1 mode) clock.
If data is output on RDPn and RDNn in RZ format and the recovered
clock is output on RCLKn, the receive system interface is in Dual Rail
RZ Format mode. In this mode, the data is un-decoded and updated on
the active edge of RCLKn. RCLKn outputs a 1.544 MHz (in T1/J1 mode)
or 2.048 MHz (in E1 mode) clock.
If data is output on RDPn and RDNn in RZ format directly after
passing through the Slicer, the receive system interface is in Dual Rail
Sliced mode. In this mode, the data is raw sliced and un-decoded.
RMFn can be selected to indicate PRBS/ARB, LAIS, LEXZ, LBPV, LEXZ
+ LBPV, LLOS, output recovered clock (RCLK) or XOR output of positive
and negative sliced data. Refer to Chapter 3.5.7.1 RMFn Indication for
the description of RMFn.
Table-3 summarizes the multiplex pin used in different receive
system interface.
Table-3 Multiplex Pin Used in Receive System Interface
Receive System
Interface
Multiplex Pin Used On Receive System
Interface
RDn / RDPn
RDNn / RMFn
RCLKn /
RMFn
Single Rail NRZ Format
RDn 1
RMFn 2
RCLKn 3
Dual Rail NRZ Format
RDPn 1
RDNn 1
RCLKn 3
Dual Rail RZ Format
RDPn 1
RDNn 1
RCLKn 3
Dual Rail Sliced
RDPn 1
RDNn 1
RMFn 2
Note:
1. The active level on RDn, RDPn and RDNn is selected by the RD_INV bit (b3,
RCF1,...).
2. RMFn is always active high.
3. The active edge of RCLKn is selected by the RCK_ES bit (b4, RCF1,...).
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