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IDT82P2288
OCTAL T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
64
March 04, 2009
3.12 BIT-ORIENTED MESSAGE RECEIVER (T1/J1
ONLY)
The Bit-Oriented Message (BOM) can only be received in the ESF
format in T1/J1 mode.
The BOM pattern is ‘111111110XXXXXX0’ which occupies the DL of
the F-bit in the ESF format (refer to
Table 13). The six ‘X’s represent the
message. The BOM is declared only when the pattern is matched and
the received message is identical 4 out of 5 consecutive times or 8 out of
10 consecutive times and differs from the previous message. The identi-
fication time is selected by the AVC bit. After a new BOM is declared, the
message is loaded into the BOC[5:0] bits. Every time when the BOC[5:0]
bits are updated, it will be indicated by the BOCI bit. A ‘1’ in the BOCI bit
means there is an interrupt. The interrupt will be reported by the INT pin
if the BOCE bit is ‘1’.
3.13 INBAND LOOPBACK CODE DETECTOR (T1/J1
ONLY)
The Inband Loopback Code Detector tracks the loopback activate/
deactivate codes only in framed or unframed T1/J1 data stream, and
meets ANSI T1.403 9.3.1.
The received data stream is compared with the target activate/deacti-
vate code whose length and content are programmed in the ASEL[1:0]/
DSEL[1:0] bits and the ACT[7:0]/DACT[7:0] bits respectively. In framed
mode, the F-bit is selected by the IBCDIDLE bit to compare with the
target activate/deactivate code or not. In unframed mode, all 193 bits are
compared with the target activate/deactivate code.
After four consecutive correct activate/deactivate codes are found in
the received data stream, the Inband Loopback Code Detector keeps on
monitoring the bit error, i.e., the bit differs from the target activate/deacti-
vate code. If in more than 126 consecutive 39.8ms fixed periods, less
than 600 bit errors are detected in each 39.8ms, the activate/deactivate
code is detected and the corresponding LBA/LBD bit will indicate it.
Once more than 600 bit errors are detected in a 39.8ms fixed period, the
activate/deactivate code is out of synchronization and the corresponding
LBA/LBD bit will be cleared. However, even if the F-bit is compared,
whether it is matched or not, the result will not cause bit errors, that is,
the comparison result of the F-bit is discarded.
Any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the LBA/LBD bit will
set the LBAI/LBDI bit, which means there is an interrupt. The interrupt
will be reported by the INT pin if the corresponding LBAE/LBDE bit is set
to ‘1’.
Bit
Register
T1/J1 Address (Hex)
AVC
BOC Control
081, 181, 281, 381, 481,
581, 681, 781
BOCE
BOC[5:0]
RBOC Code
083, 183, 283, 383, 483,
583, 683, 783
BOCI
BOC Interrupt Indication
082, 182, 282, 382, 482,
582, 682, 482
Bit
Register
T1/J1 Address (Hex)
ASEL[1:0]
IBCD Detector Configuration
076, 176, 276, 376,
476, 576, 676, 776
DSEL[1:0]
IBCDIDLE
ACT[7:0]
IBCD Activate Code
078, 178, 278, 378,
478, 578, 678, 778
DACT[7:0]
IBCD Deactivate Code
079, 179, 279, 379,
479, 579, 679, 779
LBA
IBCD Detector Status
077, 177, 277, 377,
477, 577, 677, 777
LBD
LBAI
IBCD Interrupt Indication
07B, 17B, 27B, 37B,
47B, 57B, 67B, 77B
LBDI
LBAE
IBCD Interrupt Control
07A, 17A, 27A, 37A,
47A, 57A, 67A, 77A
LBDE