Figure - 11 Transmit and Receive " />
參數(shù)資料
型號(hào): IDT821054PQF
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 37/45頁(yè)
文件大?。?/td> 0K
描述: IC PCM CODEC QUAD MPI 64-PQFP
標(biāo)準(zhǔn)包裝: 84
類型: PCM 編解碼器/濾波器
數(shù)據(jù)接口: PCM 音頻接口
ADC / DAC 數(shù)量: 4 / 4
三角積分調(diào)變: 無(wú)
電壓 - 電源,模擬: 4.75 V ~ 5.25 V
電壓 - 電源,數(shù)字: 4.75 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-QFP
供應(yīng)商設(shè)備封裝: 64-PQFP(14x14)
包裝: 管件
其它名稱: 821054PQF
42
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
8.3
PCM INTERFACE TIMING
Figure - 11 Transmit and Receive Timing
Figure - 12 Typical Frame Sync Timing (2 MHz Operation)
Symbol
Description
Min.
Typ.
Max.
Units
Test Conditions
t21
Data enable delay time
5
70
ns
t22
Data delay time from BCLK
5
70
ns
t23
Data float delay time
5
70
ns
t24
Frame sync setup time
25
t4
50
ns
t25
Frame sync hold time
50
ns
t26
TSX1 or TSX2 enable delay time
5
80
ns
t27
TSX1 or TSX2 disable delay time
5
80
ns
t28
Receive data setup time
25
ns
t29
Receive data hold time
5
ns
1234
56781
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT
1
BIT
2
BIT
3
BIT
4
BIT
5
BIT
6
BIT
7
BIT
8
BCLK
FS
DX1/
DX2
DR1/
DR2
t25
t24
Time Slot
t23
t22
t21
t28
t29
TSX1 /
TSX2
t26
t27
Note: This timing diagram only applies to the situation of receiving data on falling edges and transmitting data on rising edges.
27
28
29
30
31
01234
56789
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
X0
X1
X2
X3
R0
R1
R2
R3
Time Slot
FS
DX1/DX2
DR1/DR2
TSX1 / TSX2
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參數(shù)描述
IDT821054PQFG 功能描述:IC PCM CODEC QUAD MPI 64-PQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率(位):18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比,標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源,模擬:2.6 V ~ 3.3 V 電壓 - 電源,數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP(7x7) 包裝:帶卷 (TR)
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