參數(shù)資料
型號： IDT821054PQF
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 21/45頁
文件大?。?/td> 0K
描述： IC PCM CODEC QUAD MPI 64-PQFP
標(biāo)準(zhǔn)包裝： 84
類型： PCM 編解碼器/濾波器
數(shù)據(jù)接口： PCM 音頻接口
ADC / DAC 數(shù)量： 4 / 4
三角積分調(diào)變： 無
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 4.75 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-QFP
供應(yīng)商設(shè)備封裝： 64-PQFP（14x14）
包裝： 管件
其它名稱： 821054PQF
28
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
pins respectively. When the SB3 pins of Channel 1 to Channel 4 are configured as outputs, the control data is written to these four SB3
pins via the SB3[0] to SB3[3] bits respectively.
GREG13: FSK Flag Length, Read/Write (2CH/ACH)
The flag signal is a stream of ‘1’ which is transmitted between two message bytes during Caller-ID messages transmission. The Flag
Length bits FL[7:0] determine the number of the flag bits. The flag length can be from 0 to 255 (d) bits. The default flag length is 0 (i.e.
FL[7:0] = 00H), which means that no flag signal will be transmitted.
GREG14: FSK Data Length, Read/Write (2DH/ADH)
The Data Length bits DL[7:0] determine the number of the data bytes that will be transmitted except the flag signal. The data length can
be from 0 to
64 (d) bytes. Any value larger than 64 (d) in this register will be taken as 64 (d) by the CODEC. The default data length is 0
(d), which means that no data bytes will be transmitted.
GREG15: FSK Seizure Length, Read/Write (2EH/AEH)
The Seizure Length is the number of ‘01’ pairs that represent the seizure phase. The Seizure Length is two times of the value of the
SL[7:0] bits. The value of the SL[7:0] bits can be from 0 to 255 (d), corresponding to Seizure Length of 0 to 510 (d). The default value is
0 (d), which means that no seizure signal will be transmitted.
GREG16: FSK Mark Length, Read/Write (2FH/AFH)
The Mark Length bits ML[7:0] determine the number of the mark bits of ‘1’, which is transmitted in initial flag phase. The Mark Length can
be from 0 to 255 (d). The default value is 0 (d), which means that no mark signal will be transmitted.
GREG17: FSK Start, Mark After Send, BT/Bellcore Selection, FSK Channel Selection and FSK On/Off, Read/Write (30H/B0H)
The FSK Channel Select bits (FCS[1:0]) select a channel on which the FSK signal is generated.
FCS[1:0] = 00:
Channel 1 is selected (default);
FCS[1:0] = 01:
Channel 2 is selected;
FCS[1:0] = 10:
Channel 3 is selected;
FCS[1:0] = 11:
Channel 4 is selected.
The FSK On/Off bit (FO) enables or disables the FSK function block.
FO = 0:
The FSK function block is disabled (default);
b7
b6
b5
b4
b3
b2
b1
b0
Command
R/W
0
1011
00
I/O data
FL[7]
FL[6]
FL[5]
FL[4]
FL[3]
FL[2]
FL[1]
FL[0]
b7
b6
b5
b4
b3
b2
b1
b0
Command
R/W
0
1011
01
I/O data
DL[7]
DL[6]
DL[5]
DL[4]
DL[3]
DL[2]
DL[1]
DL[0]
b7
b6
b5
b4
b3
b2
b1
b0
Command
R/W
0
1011
10
I/O data
SL[7]
SL[6]
SL[5]
SL[4]
SL[3]
SL[2]
SL[1]
SL[0]
b7
b6
b5
b4
b3
b2
b1
b0
Command
R/W
0
1011
11
I/O data
ML[7]
ML[6]
ML[5]
ML[4]
ML[3]
ML[2]
ML[1]
ML[0]
b7
b6
b5
b4
b3
b2
b1
b0
Command
R/W
0
1100
00
I/O data
Reserved
FCS[1]
FCS[0]
FO
BS
MAS
FS
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IDT821054PQFG 功能描述:IC PCM CODEC QUAD MPI 64-PQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
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