參數資料
型號: IDT821054PQF
廠商: IDT, Integrated Device Technology Inc
文件頁數: 17/45頁
文件大?。?/td> 0K
描述: IC PCM CODEC QUAD MPI 64-PQFP
標準包裝: 84
類型: PCM 編解碼器/濾波器
數據接口: PCM 音頻接口
ADC / DAC 數量: 4 / 4
三角積分調變:
電壓 - 電源,模擬: 4.75 V ~ 5.25 V
電壓 - 電源,數字: 4.75 V ~ 5.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-QFP
供應商設備封裝: 64-PQFP(14x14)
包裝: 管件
其它名稱: 821054PQF
24
IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
INDUSTRIAL TEMPERATURE RANGE
For the global and local registers described below, it should be noted that:
1. R/W = 0, Read command. R/W = 1, Write command.
2. The reserved bit(s) in the registers must be filled in ‘0’ in write operation and be ignored in read operation.
3.4.2
GLOBAL REGISTERS LIST
GREG1: No Operation, Write (A0H); Version Number, Read (20H)
By applying a read operation (20H) to this register, users can read out the version number of the IDT821054. The default value is 01H.
To write to this register (no operation), a data byte of FFH must follow the write command (A0H) to ensure proper operation.
GREG2: Interrupt Clear, Write Only (A1H)
All interrupts on SLIC I/O will be cleared by applying a write operation to this register. Note that a data byte of FFH must follow the write
command (A1H) to ensure proper operation.
GREG3: Software Reset, Write Only (A2H)
A write operation to this register resets all local registers, but does not reset global registers and RAM. Note that when writing to this
register, a data byte of FFH must follow the write command (A2H) to ensure proper operation.
GREG4: Hardware Reset, Write Only (A3)
A write operation to this register is equivalent to setting the RESET pin to logic low (Refer to “3.3 Default State After Reset” on page 21
for details). Note that when applying this write command, a data byte of FFH must follow to ensure proper operation.
GREG5: Chopper Clock Selection, Read/Write (24H/A4H)
This register is used to select the frequency of the CHclk2 and CHclk1 output signals.
CHclk2[1:0] = 00:
the output of chclk2 is set to high permanently (default);
CHclk2[1:0] = 01:
chclk2 outputs a digital signal with the frequency of 512 kHz;
CHclk2[1:0] = 10:
chclk2 outputs a digital signal with the frequency of 256 kHz;
CHclk2[1:0] = 11:
chclk2 outputs a digital signal with the frequency of 16384 kHz;
CHclk1[3:0] = 0000:
the output of chclk1 is set to high permanently (default);
CHclk1[3:0] = 0001:
chclk1 outputs a digital signal with the frequency of 1000/2 Hz;
CHclk1[3:0] = 0010:
chclk1 outputs a digital signal with the frequency of 1000/4 Hz;
CHclk1[3:0] = 0011:
chclk1 outputs a digital signal with the frequency of 1000/6 Hz;
CHclk1[3:0] = 0100:
chclk1 outputs a digital signal with the frequency of 1000/8 Hz;
CHclk1[3:0] = 0101:
chclk1 outputs a digital signal with the frequency of 1000/10 Hz;
CHclk1[3:0] = 0110:
chclk1 outputs a digital signal with the frequency of 1000/12 Hz;
CHclk1[3:0] = 0111:
chclk1 outputs a digital signal with the frequency of 1000/14 Hz;
b7
b6
b5
b4
b3
b2
b1
b0
Command
R/W
0
1000
00
b7
b6
b5
b4
b3
b2
b1
b0
Command
10
1000
01
b7
b6
b5
b4
b3
b2
b1
b0
Command
10
1000
10
b7
b6
b5
b4
b3
b2
b1
b0
Command
10
1000
11
b7
b6
b5
b4
b3
b2
b1
b0
Command
R/W
0
1001
00
I/O data
Reserved
Chclk2[1]
Chclk2[0]
Chclk1[3]
Chclk1[2]
Chclk1[1]
Chclk1[0]
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