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參數(shù)資料
| 型號： | IDT723614L15PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS SyncBiFIFOO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2 |
| 中文描述： | 64 X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP120 |
| 封裝： | TQFP-120 |
| 文件頁數(shù)： | 7/39頁 |
| 文件大?。?/td> | 499K |
| 代理商： | IDT723614L15PF |
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7
COMMERCIAL TEMPERATURE RANGE
IDT723614 CMOS SyncBiFIFO
WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
CSB
H
L
L
L
L
L
L
L
W/
R
B
X
H
H
H
L
L
L
L
ENB
X
L
H
H
L
H
L
H
SIZ1, SIZ0
X
X
One, both LOW
Both HIGH
One, both LOW
One, both LOW
Both HIGH
Both HIGH
CLKB
X
X
↑
↑
X
↑
X
↑
B0-B35 Outputs
In High-Impedance State
In High-Impedance State
In High-Impedance State
In High-Impedance State
Active, FIFO1 Output Register
Active, FIFO1 Output Register
Active, Mail1 Register
Active, Mail1 Register
Port Functions
None
None
FIFO2 Write
Mail2 Write
None
FIFO1 read
None
Mail1 Read (Set
MBF1
HIGH)
CSA
H
L
L
L
L
L
L
L
W/
R
A
X
H
H
H
L
L
L
L
ENA
X
L
H
H
L
H
L
H
MBA
X
X
L
H
L
L
H
H
CLKA
X
X
↑
↑
X
↑
X
↑
A0-A35 Outputs
In High-Impedance State
In High-Impedance State
In High-Impedance State
In High-Impedance State
Active, FIFO2 Output Register
Active, FIFO2 Output Register
Active, Mail2 Register
Active, Mail2 Register
Port Functions
None
None
FIFO1 Write
Mail1 Write
None
FIFO2 Read
None
Mail2 Read (Set
MBF2
HIGH)
ALMOST-FULL AND
ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
16
12
8
4
FS1
FS0
RST
H
H
L
L
H
L
H
L
↑
↑
↑
↑
clock that reads data from the FIFO have not elapsed since the
time the word was written. The empty flag of the FIFO is set
HIGH by the second LOW-to-HIGH transition of the synchro-
nizing clock, and the new data word can be read to the FIFO
output register in the following cycle.
A LOW-to-HIGH transition on an empty flag synchroniz-
ing clock begins the first synchronization cycle of a write if the
clock transition occurs at time t
SKEW1
or greater after the write.
Otherwise, the subsequent clock cycle can be the first syn-
chronization cycle (see Figure 13 and 14).
TABLE 2: PORT-A ENABLE FUNCTION TABLE
TABLE 1: FLAG PROGRAMMING
TABLE 3: PORT-B ENABLE FUNCTION TABLE
FULL FLAG (
The full flag of a FIFO is synchronized to the port clock
that writes data to its array. When the full flag is HIGH, a
memory location is free in the SRAM to receive new data. No
memory locations are free when the full flag is LOW and
attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, the write pointer is
incremented. The state machine that controls a full flag
monitors a write-pointer and read-pointer comparator that
indicates when the FIFO SRAM status is full, full-1, or full-2.
From the time a word is read from a FIFO, the previous
memory location is ready to be written in a minimum of three
cycles of the full flag synchronizing clock. Therefore, a full flag
is LOW if less than two cycles of the full flag synchronizing
clock have elapsed since the next memory write location has
been read. The second LOW-to-HIGH transition on the full
flag synchronization clock after the read sets the full flag
HIGH and the data can be written in the following clock cycle.
A LOW-to-HIGH transition on a full flag synchronizing
clock begins the first synchronization cycle of a read if the
clock transition occurs at time t
SKEW1
or greater after the read.
Otherwise, the subsequent clock cycle can be the first syn-
chronization cycle (see Figure 15 and 16).
FFA
,
FFB
)
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| IDT723614L15PF8 | 功能描述:IC FIFO CLOCKED 64X36X2 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723614L15PQF | 功能描述:IC FIFO CLOCKED 64X36X2 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723614L20PF | 功能描述:IC FIFO CLOCKED 64X36X2 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723614L20PF8 | 功能描述:IC FIFO CLOCKED 64X36X2 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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