參數(shù)資料
型號: IDT723614L15PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: CMOS SyncBiFIFOO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
中文描述: 64 X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP120
封裝: TQFP-120
文件頁數(shù): 10/39頁
文件大?。?/td> 499K
代理商: IDT723614L15PF
10
COMMERCIAL TEMPERATURE RANGE
IDT723614 CMOS SyncBiFIFO
WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE (See Figures 4 through 26)
IDT723614L15 IDT723614L20 IDT723614L30
Min.
Max.
Min.
66.7
15
20
6
8
6
8
4
5
Symbol
f
S
t
CLK
t
CLKH
t
CLKL
t
DS
Parameter
Max.
50
Min.
30
12
12
6
Max.
33.4
Unit
MHz
ns
ns
ns
ns
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA and CLKB HIGH
Pulse Duration, CLKA and CLKB LOW
Setup Time, A0-A35 before CLKA
and B0-B35
before CLKB
Setup Time,
CSA
, W/
R
A, ENA and MBA before
CLKA
;
CSB
,W/
R
B and ENB before CLKB
Setup Time, SIZ0, SIZ1,and
BE
before CLKB
Setup Time, SW0 and SW1 before CLKB
Setup Time, ODD/
EVEN
and PGA before
CLKA
; ODD/
EVEN
and PGB before CLKB
(1)
Setup Time,
RST
LOW before CLKA
or CLKB
(2)
Setup Time, FS0 and FS1 before
RST
HIGH
Hold Time, A0-A35 after CLKA
and B0-B35
after CLKB
Hold Time,
CSA
, W/
R
A, ENA and MBA after
CLKA
;
CSB,
W/
R
B, and ENB after CLKB
Hold Time, SIZ0, SIZ1, and
BE
after CLKB
Hold Time, SW0 and SW1 after CLKB
Hold Time, ODD/
EVEN
and PGA after CLKA
;
ODD/
EVEN
and PGB after CLKB
(1)
Hold Time,
RST
LOW after CLKA
or CLKB
(2)
Hold Time, FS0 and FS1 after
RST
HIGH
Skew Time, between CLKA
and CLKB
for
EFA
,
EFB
,
FFA
, and
FFB
Skew Time, between CLKA
and CLKB
for
AEA
,
AEB
,
AFA
, and
AFB
t
ENS
5
5
6
ns
t
SZS
t
SWS
t
PGS
4
5
4
5
7
5
6
8
6
ns
ns
ns
t
RSTS
5
6
7
ns
t
FSS
t
DH
5
1
6
1
7
1
ns
ns
t
ENH
1
1
1
ns
t
SZH
t
SWH
t
PGH
2
0
0
2
0
0
2
0
0
ns
ns
ns
t
RSTH
t
FSH
t
SKEW1
(3)
5
4
8
6
4
8
7
4
10
ns
ns
ns
t
SKEW2
(3)
9
16
20
ns
NOTES:
1.
2.
3.
Only applies for a clock edge that does a FIFO read.
Requirement to count the clock edge as one of at least four needed to reset a FIFO.
Skew time is not a timimg constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and
CLKB cycle.
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