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參數(shù)資料
| 型號： | IDT723614L15PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS SyncBiFIFOO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2 |
| 中文描述： | 64 X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP120 |
| 封裝： | TQFP-120 |
| 文件頁數(shù)： | 16/39頁 |
| 文件大?。?/td> | 499K |
| 代理商： | IDT723614L15PF |
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16
COMMERCIAL TEMPERATURE RANGE
IDT723614 CMOS SyncBiFIFO
WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
A18-A26, and A27-A35. Port B bytes are arranged as B0-B8,
B9-B17, B18-B26, and B27-B35, and its valid bytes are those
used in a port B bus-size implementation. When odd/even
parity is selected, a port parity error flag (
PEFA
,
PEFB
) is LOW
if any byte on the port has an odd/even number of LOW levels
applied to the bits.
The four parity trees used to check the A0-A35 inputs are
shared by the mail2 register when parity generation is se-
lected for port A reads (PGA = HIGH). When a port A read from
the mail2 register with parity generation is selected with
CSA
LOW, ENA HIGH, W/
R
A LOW, MBA HIGH, and PGA HIGH,
the port A parity error flag (
PEFA
) is held HIGH regardless of
the levels applied to the A0-A35 inputs. Likewise, the parity
trees used to check the B0-B35 inputs are shared by the mail1
register when parity generation is selected for port B reads
(PGB = HIGH). When a port B read from the mail1 register with
parity generation is selected with
CSB
LOW, ENB HIGH, W/
R
B LOW, both SIZ0 and SIZ1 HIGH, and PGB HIGH, the port
B parity error flag (
PEFB
) is held HIGH regardless of the levels
applied to the B0-B35 inputs.
PARITY GENERATION
A HIGH level on the port A parity generate select (PGA)
or port B parity generate select (PGB) enables the IDT723614
to generate parity bits for port reads from a FIFO or mailbox
register. Port A bytes are arranged as A0-A8, A9-A17, A18-
26, and A27-A35, with the most significant bit of each byte
used as the parity bit. Port B bytes are arranged as B0-B8, B9-
B17, B18-B26, and B27-B35, with the most significant bit of
each byte used as the parity bit. A write to a FIFO or mail
register stores the levels applied to all nine inputs of a byte
regardless of the state of the parity generate select (PGA,
PGB) inputs. When data is read from a port with parity
generation selected, the lower eight bits of each byte are used
to generate a parity bit according to the level on the ODD/
EVEN
select. The generated parity bits are substituted for the
levels originally written to the most significant bits of each byte
as the word is read to the data outputs.
Parity bits for FIFO data are generated after the data is
read from SRAM and before the data is written to the output
register. Therefore, the port A parity generate select (PGA)
and odd/even parity select (ODD/
EVEN
) have setup and hold
time constraints to the port A clock (CLKA) and the port B
parity generate select (PGB) and ODD/
EVEN
have setup and
hold-time constraints to the port B clock (CLKB). These timing
constraints only apply for a rising clock edge used to read a
new long word to the FIFO output register.
The circuit used to generate parity for the mail1 data is
shared by the port B bus (B0-B35) to check parity and the
circuit used to generate parity for the mail2 data is shared by
the port A bus (A0-A35) to check parity. The shared parity
trees of a port are used to generate parity bits for the data in
a mail register when the port chip select (
CSA
,
CSB
) is LOW,
enable (ENA, ENB) is HIGH, write/read select (W/
R
A, W/
R
B)
input is LOW, the mail register is selected (MBA is HIGH for
port A; both SIZ0 and SIZ1 are HIGH for port B), and port parity
generate select (PGA, PGB) is HIGH. Generating parity for
mail register data does not change the contents of the register.
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| IDT723614L15PF8 | 功能描述:IC FIFO CLOCKED 64X36X2 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723614L15PQF | 功能描述:IC FIFO CLOCKED 64X36X2 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723614L20PF | 功能描述:IC FIFO CLOCKED 64X36X2 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723614L20PF8 | 功能描述:IC FIFO CLOCKED 64X36X2 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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