參數(shù)資料
型號(hào): IDT723614L15PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: CMOS SyncBiFIFOO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2
中文描述: 64 X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP120
封裝: TQFP-120
文件頁(yè)數(shù): 32/39頁(yè)
文件大?。?/td> 499K
代理商: IDT723614L15PF
32
COMMERCIAL TEMPERATURE RANGE
IDT723614 CMOS SyncBiFIFO
WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
NOTES:
1.
t
SKEW2
is the minimum time between a rising CLKB edge and a rising CLKA edge for
AFB
to transition HIGH in the next CLKB cycle. If the time
between the rising CLKB edge and rising CLKA edge is less than t
SKEW2
, then
AFB
may transition HIGH one CLKA cycle later than shown.
FIFO2 Write (
CSB
= LOW, W/
R
B = HIGH, MBB = LOW), FIFO2 read (
CSA
= LOW, W/
R
A = LOW, MBA = LOW).
Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte,
AFB
is set LOW by the last word or
byte read of the long word, respectively.
2.
3.
Figure 20. Timing for
AFB
when FIFO2 is Almost Full
AFA
CLKA
ENB
3146 drw 19
ENA
CLKB
1
2
t
SKEW2
t
ENS
t
ENH
t
PAF
t
ENS
t
ENH
t
PAF
[64-(X+1)] Long Words in FIFO1
(64-X) Long Words in FIFO1
(1)
NOTES:
1.
t
SKEW2
is the minimum time between a rising CLKA edge and a rising CLKB edge for
AFA
to transition HIGH in the next CLKA cycle. If the time
between the rising CLKA edge and rising CLKB edge is less than t
SKEW2
, then
AFA
may transition HIGH one CLKB cycle later than shown.
FIFO1 Write (
CSA
= LOW, W/
R
A = HIGH, MBA = LOW), FIFO1 read (
CSB
= LOW, W/
R
B = LOW, MBB = LOW).
Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, t
SKEW2
is referenced from the last
word or byte read of the long word, respectively.
2.
3.
Figure 19. Timing for
AFA
when FIFO1 is Almost Full
AFB
CLKB
ENA
3146 drw 20
ENB
CLKA
1
2
t
SKEW2
t
ENS
t
ENH
t
PAF
t
ENS
t
ENH
t
PAF
[64-(X+1)] Long Words in FIFO2
(64-X) Long Words in FIFO2
(1)
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