參數(shù)資料
型號(hào): IDT71V65903S85BQG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 512K X 18 ZBT SRAM, 8.5 ns, PBGA165
封裝: 13 X 15 MM, FPBGA-165
文件頁(yè)數(shù): 4/26頁(yè)
文件大?。?/td> 972K
代理商: IDT71V65903S85BQG
6.42
12
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Read Operation(1)
Burst Write Operation(1)
Burst Read Operation(1)
Write Operation(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2.
CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2.
CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2.
CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2.
CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Cycle
Address
R/
W
ADV/
LD
CE1(2)
CEN
BWx
OE
I/O
Comments
nA0
H
L
X
Address and Control meet setup
n+1
X
XXX
L
Q0
Contents of Address A0 Read Out
5298 tbl 13
Cycle
Address
R/
W
ADV/
LD
CE1(2)
CEN
BWx
OE
I/O
Comments
nA0
H
L
X
Address and Control meet setup
n+1
X
H
XL
Q0
Address A0 Read Out, Inc. Count
n+2
X
H
XL
Q0+1
Address A0+1 Read Out, Inc. Count
n+3
X
H
XL
Q0+2
Address A0+2 Read Out, Inc. Count
n+4
X
H
XL
Q0+3
Address A0+3 Read Out, Load A1
n+5
A1
HL
L
X
L
Q0
Address A0 Read Out, Inc. Count
n+6
X
H
XL
Q1
Address A1 Read Out, Inc. Count
n+7
A2
HL
L
X
L
Q1+1
Address A1+1 Read Out, Load A2
5298 tbl 14
Cycle
Address
R/
W
ADV/
LD
CE1(2)
CEN
BWx
OE
I/O
Comments
nA0
L
X
Address and Control meet setup
n+1
X
L
X
D0
Write to Address A0
5298 tbl 15
Cycle
Address
R/
W
ADV/
LD
CE1(2)
CEN
BWx
OE
I/O
Comments
nA0
L
X
Address and Control meet setup
n+1
X
H
X
L
X
D0
Address A0 Write, Inc. Count
n+2
X
H
X
L
X
D0+1
Address A0+1 Write, Inc. Count
n+3
X
H
X
L
X
D0+2
Address A0+2 Write, Inc. Count
n+4
X
H
X
L
X
D0+3
Address A0+3 Write, Load A1
n+5
A1
L
LLL
X
D0
Address A0 Write, Inc. Count
n+6
X
H
X
L
X
D1
Address A1 Write, Inc. Count
n+7
A2
L
LLL
X
D1+1
Address A1+1 Write, Load A2
5298 tbl 16
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