- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄296205 > IDT7025S55GG (INTEGRATED DEVICE TECHNOLOGY INC) 8K X 16 DUAL-PORT SRAM, 55 ns, CPGA84 PDF資料下載
參數(shù)資料
| 型號： | IDT7025S55GG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 8K X 16 DUAL-PORT SRAM, 55 ns, CPGA84 |
| 封裝： | CERAMIC, PGA-84 |
| 文件頁數(shù)： | 10/22頁 |
| 文件大?。?/td> | 176K |
| 代理商： | IDT7025S55GG |
6.42
IDT7025S/L
High-Speed 8K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
18
Functional Description
The IDT7025 provides two ports with separate control, address and
I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation
inmemory.TheIDT7025hasanautomaticpowerdownfeaturecontrolled
by
CE. The CE controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected (
CE =VIH).
When a port is enabled, access to the entire memory array is permitted.
IIIIInterrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
or message center) is assigned to each port. The left port interrupt flag
(
INTL) is asserted when the right port writes to memory location 1FFE
(HEX), where a write is defined as the
CER = R/WR=VIL perTruthTable
I. The left port clears the interrupt by an address location 1FFE access
when
CEL = OEL = VIL, R/WL is a "don't care". Likewise, the right port
interruptflag(INTR)isassertedwhentheleftportwritestomemorylocation
1FFF(HEX)andtocleartheinterruptflag(
INTR),therightportmustaccess
the memory location 1FFF, The message (16 bits) at 1FFE or 1FFF is
user-defined, since it is an addressable SRAM location. If the interrupt
function is not used, address locations 1FFE and 1FFF are not used as
mailboxes,butaspartoftherandomaccessmemory.RefertoTruthTable
I for the interrupt operation.
Truth Table III — Example of Semaphore Procurement Sequence(1,2,3)
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7025.
2. There are eight semaphore flags written to via I/O0 and read from all I/0's. These eight semaphores are addressed by A0 - A2.
3.
CE = VIH, SEM = VIL, to access the semaphores. Refer to the Semaphore Read/Write Truth Table.
Truth Table II — Address BUSY
Arbitration
NOTES:
1. Pins
BUSYL and BUSYR are both outputs when the part is configured as a master. BUSY are inputs when configured as a slave. BUSYx outputs on the IDT7025
are push pull, not open drain outputs. On slaves the
BUSY asserted internally inhibits write.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either
BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when
BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when
BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Inputs
Outputs
Function
CEL
CER
A0L-A12L
A0R-A12R
BUSYL(1)
BUSYR(1)
XX
NO MATCH
H
Normal
HX
MATCH
H
Normal
XH
MATCH
H
Normal
L
MATCH
(2)
Write Inhibit(3)
2683 tbl 17
Functions
D0 - D15 Left
D0 - D15 Right
Status
No Action
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
Semaphore free
2683 tbl 18
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT707288L20PF8 | 64K X 16 DUAL-PORT SRAM, 20 ns, PQFP100 |
| IDT70V05S35 | 8K X 8 DUAL-PORT SRAM, 35 ns, CPGA68 |
| 70V05L35PF8 | 8K X 8 DUAL-PORT SRAM, 35 ns, PQFP64 |
| 70V05L20J | 8K X 8 DUAL-PORT SRAM, 20 ns, PQCC68 |
| 70V05L35PF | 8K X 8 DUAL-PORT SRAM, 35 ns, PQFP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7025S55J | 功能描述:IC SRAM 128KBIT 55NS 84PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT7025S55J8 | 功能描述:IC SRAM 128KBIT 55NS 84PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT7025S55JI | 功能描述:IC SRAM 128KBIT 55NS 84PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-MSOP 包裝:帶卷 (TR) |
| IDT7025S55JI8 | 功能描述:IC SRAM 128KBIT 55NS 84PLCC RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT7025S55PF | 功能描述:IC SRAM 128KBIT 55NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。