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參數(shù)資料
| 型號： | IDT5V49EE902NLGI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 6/33頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN PLL 500MHZ 32VFQFPN |
| 標準包裝： | 490 |
| 類型： | * |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | HCSL，LVCMOS，LVDS，LVPECL，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:7 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 500MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-VFQFPN（5x5） |
| 包裝： | 托盤 |
| 其它名稱： | 800-2582 |
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IDT5V49EE902
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE CLOCK GENERATOR
14
IDT5V49EE902
REV P 092412
Progread
Note: If the expected read command is not from the next higher register to the previous read or write command, then set a
known “read” register address prior to a read operation by issuing the following command:
Prior to Progread Command Set Register Address
The user can ignore the STOP condition above and use a repeated START condition instead, straight after the slave
acknowledgement bit (i.e., followed by the Progread command):
Progread Command Frame
Progsave
Note:
PROGWRITE is for writing to the IDT5V49EE902 registers.
PROGREAD is for reading the IDT5V49EE902 registers.
PROGSAVE is for saving all the contents of the IDT5V49EE902 registers to the EEPROM.
PROGRESTORE is for loading the entire EEPROM contents to the IDT5V49EE902 registers.
Progrestore
EEPROM Interface
The IDT5V49EE902 can also store its configuration in an internal EEPROM. The contents of the device's internal
programming registers can be saved to the EEPROM by issuing a save instruction (ProgSave) and can be loaded back to
the internal programming registers by issuing a restore instruction (ProgRestore).
To initiate a save or restore using I2C, only two bytes are transferred. The Device Address is issued with the read/write bit
set to “0”, followed by the appropriate command code. The save or restore instruction executes after the STOP condition is
issued by the Master, during which time the IDT5V49EE902 will not generate Acknowledge bits. The IDT5V49EE902 will
acknowledge the instructions after it has completed execution of them. During that time, the I2C bus should be interpreted
as busy by all other users of the bus.
On power-up of the IDT5V49EE902, an automatic restore is performed to load the EEPROM contents into the internal
programming registers. The IDT5V49EE902 will be ready to accept a programming instruction once it acknowledges its 7-bit
I2C address.
SAddress
R/W
ACK
Command Code
ACK
Register
ACK
P
7-bits
0
1-bit
8-bits: xxxx xx00
1-bit
8-bits
1-bit
SAddress
R/W
ACK
ID Byte
ACK
Data_1
ACK
Data_2
ACK
Data_last
NACK
P
7-bits
1
1-bit
8-bits
1-bit
8-bits
1-bit
8-bits
1-bit
8-bits
1-bit
SAddress
R/W
ACK
Command Code
ACK
P
7-bits
0
1-bit
8-bits: xxxx xx01
1-bit
SAddress
R/W
ACK
Command Code
ACK
P
7-bits
0
1-bit
8-bits: xxxx xx10
1-bit
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT5V49EE902NLGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN EEPROM PROGR 32QFN |
| IDT5V49EE903NLGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GENERATOR |
| IDT5V49EE903NLGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN EEPROM PROGR 32QFN |
| IDT5V49EE903PGGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GENERATOR |
| IDT5V49EE903PGGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN EEPROM PROGR 28TSSOP |
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