參數(shù)資料
型號(hào)： IDT5V49EE902NLGI
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 4/33頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN PLL 500MHZ 32VFQFPN
標(biāo)準(zhǔn)包裝： 490
類型： *
PLL： 帶旁路
輸入： LVCMOS，LVTTL，晶體
輸出： HCSL，LVCMOS，LVDS，LVPECL，LVTTL
電路數(shù)： 1
比率 - 輸入:輸出： 3:7
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 500MHz
除法器/乘法器： 是/是
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-VFQFPN（5x5）
包裝： 托盤
其它名稱： 800-2582
IDT5V49EE902
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE CLOCK GENERATOR
12
IDT5V49EE902
REV P 092412
SEL[2:0] Function
The IDT5V49EE902 can support up to six unique
configurations. Users may pre-programmed all these
configurations, and select the configurations using SEL[2:0]
pins. Alternatively, users may use I2C interface to configure
these registers on-the-fly.
Crystal/Clock Selection
XTCLKSEL bit is used to bypass a crystal oscillator circuit
when external clock source is used.
PRIMSRC bit is used to select a primary clock from
XIN/REF and CLKIN.
SD/OE Pin Function
The polarity of the SD/OE signal pin can be programmed to
be either active HIGH or LOW with the SP bit (0x02). When
SP is “0” (default), the pin becomes active LOW and when
SP is “1”, the pin becomes active HIGH. The SD/OE pin can
be configured as either to shutdown the PLLs or to
enable/disable the outputs.
Configuration OUTx IO Standard
Users can configure the individual output IO standard from
a specified 1.8V to 3.3V power supplies. Each output can
support 1.8V to 3.3V LVTTL. Each output pair can support
LVDS, LVPECL or HCSL from the specified 3.3V power
supply. OUT0 can only be 3.3V single-ended output.
SEL2
SEL1
SEL0
Configuration Selections
0
Select CONFIG0
0
1
Select CONFIG1
0
1
0
Select CONFIG2
0
1
Select CONFIG3
1
0
Select CONFIG4
1
0
1
Select CONFIG5
1
0
Reserved (Do not use)
1
Reserved (Do not use)
PRIMSRC bit
Primary
Secondary
0XIN/REF
CLKIN
1
CLKIN
XIN/REF
CLKSEL input
0
1
CLKSEL
PRIMSRC Reference Clock
0
XIN/REF
01
CLKIN
10
CLKIN
1
XIN/REF
Clock Source
Primary Clock Source
Secondary Clock Source
SMx[1:0] Swithcing Mode
Primary to
Secondary
Secondary to
Primary
0x
Manual
No
10
Auto
Yes
No
11
Auto-Revertive
Yes
OUTn
OS
OE
SP
SD/OE Input
SH
Global Shutdown
Truth Table
SH bit SP bit OSn bit OEn bit SD/OE
OUTn
0
x
High-Z
2
0
1
0
x
Enabled
0
1
0
Enabled
0
1
Suspended
0
1
0
x
High-Z
2
0
1
0
x
Enabled
0
1
0
Suspended
0
1
Enabled
1
0
x
0
High-Z
2
1
0
1
0
Enabled
1
0
1
0
Enabled
1
0
x
0
High-Z
2
1
0
Enabled
1
0
Suspended
1x
x
1
Suspended
1
Note 1 : Global Shutdown
Note 2 : Hi-Z regardless of OEM bits
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