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參數(shù)資料
| 型號： | IDT5V49EE902NLGI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 14/33頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN PLL 500MHZ 32VFQFPN |
| 標準包裝： | 490 |
| 類型： | * |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | HCSL，LVCMOS，LVDS，LVPECL，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:7 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 500MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-VFQFPN（5x5） |
| 包裝： | 托盤 |
| 其它名稱： | 800-2582 |
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IDT5V49EE902
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE CLOCK GENERATOR
21
IDT5V49EE902
REV P 092412
AC Timing Electrical Characteristics
(Spread Spectrum Generation = OFF)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
fIN
1
Input Frequency
Input frequency limit (CLKIN)
1
200
MHz
Input frequency limit (XIN/REF)
8
100
MHz
1 / t1
Output Frequency
Single ended clock output limit (LVTTL)
0.001
200
MHz
Differential clock output limit (LVPECL/
LVDS/HCSL)
0.001
500
fVCO
VCO Frequency
VCO operating frequency range
100
1300
MHz
fPFD
PFD Frequency
PFD operating frequency range
0.5 1
100
MHz
fBW
Loop Bandwidth
Based on loop filter resistor and capacitor
values
0.01
10
MHz
t2
Input Duty Cycle
Duty Cycle for input
40
60
%
t3
Output Duty Cycle
Measured at VDD/2, all outputs except
Reference output
45
55
%
Measured at VDD/2, Reference output
40
60
%
t4 2
Slew Rate, SLEW[1:0] = 00
Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of VDD
(Output Load = 5 pF)
3.5
V/ns
Slew Rate, SLEW[1:0] = 01
Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of VDD
(Output Load = 5 pF)
2.75
Slew Rate, SLEW[1:0] = 10
Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of VDD
(Output Load = 5 pF)
2
Slew Rate, SLEW[1:0] = 11
Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of VDD
(Output Load = 5 pF)
1.25
t5
Rise Times
LVDS, 20% to 80%
600
ps
Fall Times
LVDS, 80% to 20%
600
Rise Times
LVPECL, 20% to 80%
600
ps
Fall Times
LVPECL, 80% to 20%
600
Rise Times
HCSL, From 0.175 V to 0.525 V
175
400
700
ps
Fall Times
HCSL, From 0.525 V to 0.175 V
175
400
700
t7
Clock Jitter
Peak-to-peak period jitter, 1PLL, multiple
output frequencies switching, LVTTL outputs
80
100
ps
Peak-to-peak period jitter, all 4 PLLs on,
LVTTL outputs3
200
270
ps
Peak-to-peak period jitter, 1PLL, multiple
output frequencies switching, LVPECL, LVDS
or HCSL outputs
60
80
ps
Peak-to-peak period jitter, all 4 PLLs on,
LVPECL, LVDS or HCSL outputs
120
160
ps
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| IDT5V49EE902NLGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN EEPROM PROGR 32QFN |
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