參數(shù)資料
型號(hào)： IDT5V49EE902NLGI
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 3/33頁(yè)
文件大小： 0K
描述： IC CLOCK GEN PLL 500MHZ 32VFQFPN
標(biāo)準(zhǔn)包裝： 490
類型： *
PLL： 帶旁路
輸入： LVCMOS，LVTTL，晶體
輸出： HCSL，LVCMOS，LVDS，LVPECL，LVTTL
電路數(shù)： 1
比率 - 輸入:輸出： 3:7
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 500MHz
除法器/乘法器： 是/是
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-VFQFPN（5x5）
包裝： 托盤(pán)
其它名稱： 800-2582
IDT5V49EE902
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE CLOCK GENERATOR
11
IDT5V49EE902
REV P 092412
PLL Loop Bandwidth:
Charge pump gain (K
φ) = Ip / 2π
VCO gain (KVCO) = 900 MHz/V * 2
π
M = Total multiplier value (See the Reference Divider,
Feedback Divider and Output Divider section for more
detail)
ωc = (Rz * Kφ * KVCO * Cz)/(M * (Cz + Cp))
Fc =
ωc / 2π
Note, the phase/frequency detector frequency (FPFD) is
typically seven times the PLL closed-loop bandwidth (Fc)
but too high of a ratio will reduce the phase margin thus
compromising loop stability.
To determine if the loop is stable, the phase margin (
φm)
needs to be calculated as follows.
Phase Margin:
ωz = 1 / (Rz * Cz)
ωp = (Cz + Cp)/(Rz * Cz * Cp)
φm = (360 / 2π) * [tan-1(ωc/ ωz) - tan-1(ωc/ ωp)]
To ensure stability in the loop, the phase margin is
recommended to be > 60° but too high will result in the lock
time being excessively long. Certain loop filter parameters
would need to be compromised to not only meet a required
loop bandwidth but to also maintain loop stability.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT5V49EE902NLGI8 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN EEPROM PROGR 32QFN
IDT5V49EE903NLGI 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GENERATOR
IDT5V49EE903NLGI8 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN EEPROM PROGR 32QFN
IDT5V49EE903PGGI 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GENERATOR
IDT5V49EE903PGGI8 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN EEPROM PROGR 28TSSOP
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